Intel Celeron

By : http://en.wikipedia.org/


Celeron


Produced:April 1998
Manufacturer:Intel
CPU Speeds:266 MHz to 3.60 GHz
FSB Speeds:66 MHz to 200 MHz
Process:(MOSFET channel length)0.25 µm to 0.065 µm
Instruction Set:x86, x86-64
Microarchitecture:P6, NetBurst, Core
Sockets:
· Slot 1
· Socket 370
· Socket 478
· LGA 775
Cores:
· Covington
· Mendocino
· Coppermine-128
· Tualatin-256
· Willamette-128
· Northwood-128
· Prescott-256


Celeron


Celeron is a brand name given by Intel Corp. to a large number of different x86 microprocessor models that they produced and marketed as a budget/value CPU line. The Celeron family complements Intel's higher-performance (and more expensive) product lines (currently Core 2 Duo and formerly Pentium). Introduced in April 1998, the first Celeron was based on the Pentium II core. Later versions were based on the Pentium III, Pentium 4,Pentium M, and Core 2 Duo. These processors are suitable for most applications, but their performance is somewhat limited when it comes to running intense applications, such as cutting edge games or graphical modeling programs, as compared to that of their high-end counterparts.
As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to Cyrix's 6x86, AMD's K6, and IDT Winchip. Intel's existing low-end product, the Pentium MMX, was no longer performance competitive at 233MHz[3]. Although a faster Pentium MMX would have been a lower-risk strategy, the industry standard Socket 7 platform hosted a market of competitor CPUs which could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part that was pin-compatible with their high-end Pentium II product, using the Pentium II's (Slot 1) interface. The Celeron was used in many low end machines and, in some ways, became the standard for non gaming computers.

Celeron (P6)
Covington
The first Celeron (codenamed Covington) was essentially a 266 MHz Deschutes Pentium II manufactured without any secondary cache at all. Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz (Frequencies 33 to 66 MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons were a good deal slower than the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. The initial market interest faded rapidly in the face of its poor performance and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless the first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in slot 1 SEPP format.
The Mendocino Celeron, launched August 24th, 1998, was the first mass-market CPU to utilise on-die L2 cache. Where as Covington had no secondary cache at all, Mendocino included 128 KiB of L2 cache running at full clock speed. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clockspeed. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A. Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an A appended, some people call all Mendocino processors "Celeron-A" regardless of speed.
The new Mendocino core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as too successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, the Celeron 300A could run reliably at 450 MHz. This was achieved by simply increasing the Front Side Bus (FSB) speed from the stock 66 MHz to the 100 MHz spec of the Pentium II. At this speed, the Mendocino Celeron rivaled the fastest x86 processors available.
At the time on-die cache was difficult to manufacture; especially L2 as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock frequency as the CPU. All other CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 KiB or 1 MiB), but they carried the performance penalty of slower cache speed, typically running at FSB speed (60 to 100 MHz) for motherboard mounted L2 cache. The implementation of the Pentium II's 512 KiB of L2 cache was unique at the time (and later copied by AMD's Athlon), being comprised of moderately high-speed L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half processor speed and communicating with the CPU through a special backside bus. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked faster and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.
Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The "Mendocino" Celeron CPU came only designed for a 66 MHz frontside bus, but this would not be a serious performance bottleneck until clock speeds reached higher levels.
The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant: beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed Slotkets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is that SMP (symmetric multiprocessing) mode was available, and there was at least one motherboard released (the ABIT BP6) which took advantage of this fact.
The Mendocino also came in a mobile variant, with speeds from 266, 300, 333, 366, 400, 433, and 466, 500, 533, 566, 600 MHz.
In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related Dixon Mobile Pentium II variant.
The next generation Celeron was the Coppermine-128 (sometimes known as the "Celeron II"). These were a derivative of Intel's Coppermine Pentium III and were released on March 29th, 2000[12]. Like the Mendocino, the Celeron-128 used 128 KiB of on-chip L2 cache and was (initially) restricted to a 66 MHz bus speed, but the big news was the addition of SSE instructions, due to the new Coppermine core. Other than half the L2 cache (128 KiB instead of 256 KiB) and a slower FSB (66 to 100 MHz instead of 100 to 133 MHz), the Coppermine Celeron was identical to the Coppermine Pentium III.
All Coppermine-128s were produced in the same FCPGA Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533 MHz and continued through 566, 600, 633, 666, 700, 733, and 766 MHz. Because of the limitations of the 66 MHz bus, there were diminishing returns on performance as clock rate increased. On January 3, 2001, Intel switched to a 100 MHz bus with the launch of the 800 MHz Celeron, resulting in a significant performance-per-clock improvement[13]. All Celeron-128 CPUs from 800 MHz and faster use the 100 MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100 MHz.
In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526.
Tualatin-256
These Celeron processors, released initially at 1200 MHz (1.2 GHz) on October 2nd, 2001[14], were based on Pentium III Tualatin core and made with a 0.13 micrometer process for the FCPGA2 socket 370 . They were nicknamed "Tualeron" — a portmanteau of the words Tualatin and Celeron. Some software and users refer to the chips as "Celeron-S", referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1000 MHz and 1100 MHz parts (which were given the extension "A" to their name to differentiate them from the Coppermine-128 of the same speed they replaced)[15]. A 1300 MHz chip, launched January 4, 2002[16], and finally a 1400 MHz chip, launched May 15, 2002 (the same day as the Netburst Williamette 1.7 GHz Celeron launch)[17], marked the end of the Tualatin-256 line.
With regards to core functionality, Tualatin-256 was again quite similar to its Pentium III sibling. The most significant difference was the slower 100 MHz bus, it and had only 256 KiB of L2 cache (where as the Pentium III had either 256 KiB or 512 KiB of L2 cache). Furthermore, the Tualeron's L2 cache had a higher latency which boosted manufacturing yields for this budget CPU.
Despite offering much improved performance over the Coppermine Celeron it superceded, the Tualatin Celeron still suffered stiff competition from AMD's Duron budget processor[18]. Intel later responded by releasing the Netburst Williamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with their replacement Pentium 4-based Celerons.
In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530.
Celeron (NetBurst)
Willamette-128
These Celerons were for socket 478 and were based on the Willamette Pentium 4 core, being a completely different design compared to the previous Tualatin Celeron. These are often known as the "Celeron 4". Their L2 cache (128 KiB) is half that of the Pentium 4 Williamette's 256 KiB of L2 cache, but otherwise the two are very similar. With the transition to the Pentium 4 core the Celeron now featured SSE2 instructions. The ability to share the same socket as the Pentium 4 meant that the Celeron now had the option to use RDRAM, DDR SDRAM, or traditional SDRAM. Williamette Celerons were launched May 15, 2002, initially at 1.7GHz, and offered a noticeable performance improvement over the older Tualatin Celeron 1300 MHz part, being able to finally best the Duron 1.3 GHz, which at the time was AMD's top competing budget processor. On June 12th, 2002, Intel launched the last Williamette Celeron, a 1.8GHz model.
In Intel's "Family/Model/Stepping" scheme, Willamette Celerons and Pentium 4s are family 15, model 1, and their Intel product code is 80531.
Northwood-128
These socket 478 Celerons are based on the Northwood Pentium 4 core, and also have 128 KiB of L2 cache. The only difference between the Northwood-128 and the Willamette-128 Celeron is the fact that it was built on the new 0.13 micrometre process which shrunk the die size, increased the transistor count, and lowered the core voltage from 1.7 V on the Willamette-128 to 1.52 V for the Northwood-128. Despite these differences, they are functionally the same as the Willamette-128 Celeron, and perform largely the same clock-for-clock. The Northwood-128 family of processors were initially released as a 2.0 GHz Model (a 1.9GHz model was announced earlier, but never launched) on September 18th, 2002. Since that time Intel has released at total of 10 different speed grades ranging from 1.8GHz to 2.8GHz, before being surpassed by the Celeron D. Although the Northwood Celerons suffer considerably from their small L2 cache, some speed grades have been favored in the enthusiast market, because like the old 300A, they can run well above their rated speeds.
In Intel's "Family/Model/Stepping" scheme, Northwood Celerons and Pentium 4s are family 15, model 2, and their Intel product code is 80532.

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Intel Celeron

By : http://en.wikipedia.org

Celeron

Produced:April 1998
Manufacturer:Intel
CPU Speeds:266 MHz to 3.60 GHz
FSB Speeds:66 MHz to 200 MHz
Process:(MOSFET channel length)0.25 µm to 0.065 µm
Instruction Set:x86, x86-64
Microarchitecture:P6, NetBurst, Core
Sockets:
· Slot 1
· Socket 370
· Socket 478
· LGA 775
Cores:
· Covington
· Mendocino
· Coppermine-128
· Tualatin-256
· Willamette-128
· Northwood-128
· Prescott-256

Celeron

Celeron is a brand name given by Intel Corp. to a large number of different x86 microprocessor models that they produced and marketed as a budget/value CPU line. The Celeron family complements Intel's higher-performance (and more expensive) product lines (currently Core 2 Duo and formerly Pentium). Introduced in April 1998, the first Celeron was based on the Pentium II core. Later versions were based on the Pentium III, Pentium 4,Pentium M, and Core 2 Duo. These processors are suitable for most applications, but their performance is somewhat limited when it comes to running intense applications, such as cutting edge games or graphical modeling programs, as compared to that of their high-end counterparts.
As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to Cyrix's 6x86, AMD's K6, and IDT Winchip. Intel's existing low-end product, the Pentium MMX, was no longer performance competitive at 233MHz[3]. Although a faster Pentium MMX would have been a lower-risk strategy, the industry standard Socket 7 platform hosted a market of competitor CPUs which could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part that was pin-compatible with their high-end Pentium II product, using the Pentium II's (Slot 1) interface. The Celeron was used in many low end machines and, in some ways, became the standard for non gaming computers.

Celeron (P6)
Covington
The first Celeron (codenamed Covington) was essentially a 266 MHz Deschutes Pentium II manufactured without any secondary cache at all. Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz (Frequencies 33 to 66 MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons were a good deal slower than the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. The initial market interest faded rapidly in the face of its poor performance and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless the first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in slot 1 SEPP format.
The Mendocino Celeron, launched August 24th, 1998, was the first mass-market CPU to utilise on-die L2 cache. Where as Covington had no secondary cache at all, Mendocino included 128 KiB of L2 cache running at full clock speed. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clockspeed. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A. Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an A appended, some people call all Mendocino processors "Celeron-A" regardless of speed.
The new Mendocino core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as too successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, the Celeron 300A could run reliably at 450 MHz. This was achieved by simply increasing the Front Side Bus (FSB) speed from the stock 66 MHz to the 100 MHz spec of the Pentium II. At this speed, the Mendocino Celeron rivaled the fastest x86 processors available.
At the time on-die cache was difficult to manufacture; especially L2 as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock frequency as the CPU. All other CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 KiB or 1 MiB), but they carried the performance penalty of slower cache speed, typically running at FSB speed (60 to 100 MHz) for motherboard mounted L2 cache. The implementation of the Pentium II's 512 KiB of L2 cache was unique at the time (and later copied by AMD's Athlon), being comprised of moderately high-speed L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half processor speed and communicating with the CPU through a special backside bus. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked faster and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.
Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The "Mendocino" Celeron CPU came only designed for a 66 MHz frontside bus, but this would not be a serious performance bottleneck until clock speeds reached higher levels.
The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant: beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed Slotkets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is that SMP (symmetric multiprocessing) mode was available, and there was at least one motherboard released (the ABIT BP6) which took advantage of this fact.
The Mendocino also came in a mobile variant, with speeds from 266, 300, 333, 366, 400, 433, and 466, 500, 533, 566, 600 MHz.
In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related Dixon Mobile Pentium II variant.
The next generation Celeron was the Coppermine-128 (sometimes known as the "Celeron II"). These were a derivative of Intel's Coppermine Pentium III and were released on March 29th, 2000[12]. Like the Mendocino, the Celeron-128 used 128 KiB of on-chip L2 cache and was (initially) restricted to a 66 MHz bus speed, but the big news was the addition of SSE instructions, due to the new Coppermine core. Other than half the L2 cache (128 KiB instead of 256 KiB) and a slower FSB (66 to 100 MHz instead of 100 to 133 MHz), the Coppermine Celeron was identical to the Coppermine Pentium III.
All Coppermine-128s were produced in the same FCPGA Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533 MHz and continued through 566, 600, 633, 666, 700, 733, and 766 MHz. Because of the limitations of the 66 MHz bus, there were diminishing returns on performance as clock rate increased. On January 3, 2001, Intel switched to a 100 MHz bus with the launch of the 800 MHz Celeron, resulting in a significant performance-per-clock improvement[13]. All Celeron-128 CPUs from 800 MHz and faster use the 100 MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100 MHz.
In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526.
Tualatin-256
These Celeron processors, released initially at 1200 MHz (1.2 GHz) on October 2nd, 2001[14], were based on Pentium III Tualatin core and made with a 0.13 micrometer process for the FCPGA2 socket 370 . They were nicknamed "Tualeron" — a portmanteau of the words Tualatin and Celeron. Some software and users refer to the chips as "Celeron-S", referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1000 MHz and 1100 MHz parts (which were given the extension "A" to their name to differentiate them from the Coppermine-128 of the same speed they replaced)[15]. A 1300 MHz chip, launched January 4, 2002[16], and finally a 1400 MHz chip, launched May 15, 2002 (the same day as the Netburst Williamette 1.7 GHz Celeron launch)[17], marked the end of the Tualatin-256 line.
With regards to core functionality, Tualatin-256 was again quite similar to its Pentium III sibling. The most significant difference was the slower 100 MHz bus, it and had only 256 KiB of L2 cache (where as the Pentium III had either 256 KiB or 512 KiB of L2 cache). Furthermore, the Tualeron's L2 cache had a higher latency which boosted manufacturing yields for this budget CPU.
Despite offering much improved performance over the Coppermine Celeron it superceded, the Tualatin Celeron still suffered stiff competition from AMD's Duron budget processor[18]. Intel later responded by releasing the Netburst Williamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with their replacement Pentium 4-based Celerons.
In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530.
Celeron (NetBurst)
Willamette-128
These Celerons were for socket 478 and were based on the Willamette Pentium 4 core, being a completely different design compared to the previous Tualatin Celeron. These are often known as the "Celeron 4". Their L2 cache (128 KiB) is half that of the Pentium 4 Williamette's 256 KiB of L2 cache, but otherwise the two are very similar. With the transition to the Pentium 4 core the Celeron now featured SSE2 instructions. The ability to share the same socket as the Pentium 4 meant that the Celeron now had the option to use RDRAM, DDR SDRAM, or traditional SDRAM. Williamette Celerons were launched May 15, 2002, initially at 1.7GHz, and offered a noticeable performance improvement over the older Tualatin Celeron 1300 MHz part, being able to finally best the Duron 1.3 GHz, which at the time was AMD's top competing budget processor. On June 12th, 2002, Intel launched the last Williamette Celeron, a 1.8GHz model.
In Intel's "Family/Model/Stepping" scheme, Willamette Celerons and Pentium 4s are family 15, model 1, and their Intel product code is 80531.
Northwood-128
These socket 478 Celerons are based on the Northwood Pentium 4 core, and also have 128 KiB of L2 cache. The only difference between the Northwood-128 and the Willamette-128 Celeron is the fact that it was built on the new 0.13 micrometre process which shrunk the die size, increased the transistor count, and lowered the core voltage from 1.7 V on the Willamette-128 to 1.52 V for the Northwood-128. Despite these differences, they are functionally the same as the Willamette-128 Celeron, and perform largely the same clock-for-clock. The Northwood-128 family of processors were initially released as a 2.0 GHz Model (a 1.9GHz model was announced earlier, but never launched) on September 18th, 2002. Since that time Intel has released at total of 10 different speed grades ranging from 1.8GHz to 2.8GHz, before being surpassed by the Celeron D. Although the Northwood Celerons suffer considerably from their small L2 cache, some speed grades have been favored in the enthusiast market, because like the old 300A, they can run well above their rated speeds.
In Intel's "Family/Model/Stepping" scheme, Northwood Celerons and Pentium 4s are family 15, model 2, and their Intel product code is 80532.

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Intel Centrino

By : http://en.wikipedia.org

Centrino

Components of the Centrino platform. From right, clockwise: Intel PRO/Wireless network adapter, Intel mobile processor, Intel mobile chipset (southbridge and northbridge).
Centrino, a platform-marketing initiative from Intel, covers a particular combination of CPU, mainboard chipset and wireless network interface in the design of a laptop personal computer. Intel claimed that systems equipped with these technologies should deliver better performance, longer battery life and broad wireless network interoperability. The chips were developed at Intel's Haifa, Israel R&D center and since their introduction in 2003, over US$5 billion worth have been sold.[citation needed]
To qualify for a Centrino label, laptop vendors must use all three Intel qualified parts, otherwise using only the processor and chipset will carry the Intel Core label instead.

Implementations
Carmel platform (2003)
Intel used Carmel as the code name for the first-generation Centrino platform introduced in March 2003.
The Carmel platform consists of:
an Intel Pentium M processor (code-named Banias or later Dothan) with a 400 MT/s FSB, Socket 478 and
an Intel 855 series chipset (code-named Odem or Montara with Intel Extreme Graphics 2), DDR-266 and
an Intel PRO/Wireless 2100 or later 2200 (IEEE 802.11b) mini-PCI Wi-Fi adapter (code-named Calexico or Calexico2).
Industry-watchers initially criticized the Carmel platform for its lack of an IEEE 802.11g-solution, because many independent Wi-Fi chip-makers like Broadcom and Atheros had already started shipping 802.11g products. Intel responded that the IEEE had not finalized the 802.11g standard at the time of Carmel's launch, and that it did not want to launch products not based on a finalized standard.
In early 2004, after the finalization of the 802.11g standard, Intel permitted an Intel PRO/Wireless 2200BG (code-named Calexico2) to substitute for the 2100. At the same time, they permitted the new Dothan Pentium M to substitute for the Banias Pentium M. Initially, Intel permitted only the 855GM chipset, which did not support external graphics. Later, Intel allowed the 855GME and 855PM chips, which did support external graphics, in Centrino notebooks.
Despite criticisms, the Carmel platform won quick acceptance among OEMs and consumers. Carmel could attain or exceed the performance of older Pentium 4-M platforms, while allowing for notebooks to operate for 4 to 5 hours on a 48 W-h battery. Carmel also allowed notebook-manufacturers to create thinner and lighter notebooks because its components did not dissipate much heat, and thus did not require large cooling systems.
Sonoma platform (2005)
Intel used Sonoma as the code name for the second-generation Centrino platform, introduced in January 2005.
The Sonoma platform consists of:
an Intel Pentium M processor (code-named Dothan) with a 533 MT/s FSB, Socket 479 and
an Intel Mobile 915 Express series chipset (code-named Alviso with Intel's GMA 900), DDR2-533 and
the Intel PRO/Wireless 2200 or 2915ABG mini-PCI Wi-Fi adapter (code-named Calexico2).
The Mobile 915 Express chipset, like its desktop version, supports many new features such as DDR2, PCI Express, Intel High Definition Audio, and SATA. Unfortunately, the introduction of PCI Express and faster Pentium M processors causes notebooks built around the Sonoma platform to have a shorter battery-life than their Carmel counterparts; Sonoma notebooks typically achieve between 3.5-4.5 hours of battery-life on a 53 W-h battery.
Napa platform (2006)
The code-name Napa designates the third-generation Centrino platform, introduced in January 2006 at the Winter Consumer Electronics Show. The platform initially supported Intel Core Duo processors but the newer Core 2 Duo processors were launched and supported in this platform from July 27th 2006 onwards.
The Napa platform consists of:
Processors - Socket M
an Intel Core Solo, Core Duo (code-named Yonah) processor, or
an Intel Core 2 Duo (code-named Merom) processor with a 667 MT/s FSB for Napa Refresh platform.
an Intel Mobile 945 Express-series chipset (code-named Calistoga with Intel's GMA 950), including ICH7M southbridge, and
RAM supported for DDR2-533 and DDR2-667 SODIMM.
the Intel PRO/Wireless 3945ABG mini-PCIe Wi-Fi adapter (code-named Golan), and
Some newer models (as of 1st quarter 2007) of the Napa Refresh platform contain the newer 4965AGN (a/b/g/draft-n) wireless cards.
Intel uses Centrino Duo branding for laptops with dual-core ("Core Duo") and ("Core 2 Duo") processors and retains the Centrino name for laptops with single core ("Core Solo") processors. Some of the initial Core Duo laptops, are still labeled as Intel Centrino rather than Centrino Duo.
[edit] Santa Rosa platform (2007)
The code-name Santa Rosa refers to the fourth-generation Centrino platform, which was released on Wednesday 9 May 2007.
The Santa Rosa platform consists of:
Processors - Socket P
an Intel Core 2 Duo (code-named Merom) second generation processor with 800 MT/s FSB, or
an Intel Core 2 Duo (code-named Penryn) 45nm processor scheduled for release in 1H 2008 [1] for Santa Rosa Refresh platform.
an Intel Mobile 965 Express chipset (code-named Crestline) with Intel's GMA X3100 graphics technology and ICH8M southbridge, 800 MT/s front side bus with Dynamic Front Side Bus Switching to save power during low utilization, and
Intel Dynamic Acceleration (IDA), better Windows Vista Aero support. [2]
RAM supported for DDR2-533 and DDR2-667 SODIMM.
EFI-compliant firmware, a successor to BIOS.
optional NAND flash-memory caching branded as Intel Turbo Memory (code-named Robson)
the Intel Wireless WiFi Link 4965AGN (a/b/g/draft-n) mini-PCIe Wi-Fi adapter (code-named Kedron).
Wireless-N technology boasts a 5X speed increase, along with a 2X greater coverage area, and supports 2.4 GHz and 5 GHz signal bands, with enough bandwidth for high definition audio and video streams. [1]
Santa Rosa platform come with dynamic acceleration technology. It allows single threaded applications to execute faster. When a single threaded application is running the CPU can turn off one of the CPU cores and overclock the active core. In this way the CPU maintains the same Thermal Profile as it would when both cores are active. Many expect Santa Rosa to perform well as a mobile gaming platform due to its ability to switch between single threaded and multithreaded tasks. Other power savings come from an Enhanced Sleep state where both the CPU cores and the chipset will power down.
The wireless chipset update was originally intended to include WWAN Internet access via HSDPA (3.5G), (code-named Windigo) co-developed with Nokia After announcing a working partnership, both later retracted the deal citing the lack of a clear business case for the technology.
Support for WiMAX (802.16) was originally scheduled for inclusion in Santa Rosa but appears to have been delayed until Montevina in 2008. There have, however, been reports that WiMax may still be introduced in 2007.
The Santa Rosa platform is branded as "Centrino Pro" when combined with the enhanced security technologies Intel introduced with vPro and will be called "Centrino Duo" when they are not used.
Montevina platform (2008)
The code-name Montevina refers to the fifth-generation Centrino platform, scheduled for release in Q2 2008. Montevina will support Penryn, Intel's 45nm die-shrink version of its current generation of 65nm Core 2 processors.
The code-named Penryn 45nm chip is planned to consume no more than 29W, compared to Merom's 34W TDP, the debut of SSE4.1, which will add 47 new instructions to SSSE3.
Montevina comprises the Cantiga chipset (with ICH9M southbridge) and with front side bus speed increase to 1067 MT/s front side bus. The graphics core is expected to be clocked at 475MHz which will contain ten unified shaders, up from the GMA 3000's eight.
Reports have suggested RAM support for DDR3-800 in preference to the less power-efficient DDR2-800 SODIMM.
NAND flash-memory caching branded as Intel Turbo Memory (code-named Robson 2).
LAN controller (code-named Boaz). Wireless Modules
the Intel Wireless WiFi Link mini-PCIe adapter (code-named Shiloh), and the add-on card WiMAX (802.16) (code-named Dana Point), or
the Intel combo WiFi/WiMAX Link mini-PCIe adapter (code-named Echo Peak).
Intel has reportedly invested US$300 million in Centrino advertising. Because of the ubiquity of the marketing campaign, many consumers mistakenly refer to Pentium M and Intel Core processors as "Centrinos". Many consumers have received the impression that only Centrino provides wireless connectivity in a notebook. This has resulted in increased demand for Intel's PRO/Wireless chipsets.
The Centrino marketing program has been widely assumed to be responsible for the success of Intel notebook PCs. However, findings of the Japanese FTC in March of 2005 indicate that the financial incentives associated with the Centrino program were used as illegal, anti-competitive practices by Intel to induce its customers not to buy notebook chips from Intel's long time rival AMD. In the quarter immediately following the JFTC ruling, AMD boasted more than 60 notebook computer design wins which was a strong resurgence from the drastic share reductions seen in 2003 and 2004.

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Intel Core 2

By : http://en.wikipedia.org
Core 2

Produced:
From 2006
Manufacturer:Intel
CPU Speeds:1.06 GHz to 3.0 GHz
FSB Speeds:533 MT/s to 1333 MT/s
Process:(MOSFET channel length)0.065 µm to 0.045 µm
Instruction Set:x86, MMX, SSE, SSE2, SSE3, SSSE3, x86-64
Microarchitecture:Intel Core microarchitecture
Sockets:
· Socket T (LGA 775)
· Socket M (µPGA 478)
· Socket P (uPGA 478)
Cores:
· Allendale
· Conroe
· Merom
· Kentsfield

Intel Core 2

The Core 2 brand refers to a range of Intel's mobile and desktop 64-bit dual-/quad-core x86 CPUs with the Core microarchitecture, which evolved from the 32-bit dual-core Yonah mobile processor. The Yonah comprised two interconnected single cores (the Pentium M branded microprocessor derivatives) coupled as a single die silicon chip (IC). The Core 2 marked a relegation of the Intel's Pentium brand to a lower-end market, and a reunification of Intel's notebook and desktop brand names, previously divided into the Pentium M and Pentium 4 lines.
The Core 2 brand was launched on July 27, 2006, comprising Duo (dual-core), Quad (quad-core), and Extreme (dual- or quad-core CPUs with higher speeds and unlocked multiplier) branches. The brand covers processors based on various cores; "Conroe" and "Allendale" (dual-core for higher- and lower-end desktop use, respectively), "Merom" (dual-core for notebooks), "Kentsfield" (quad-core for desktops), and their variants named "Penryn" (dual-core for notebooks), "Wolfdale" (dual-core for desktops) and "Yorkfield" (quad-core for desktops). Although the "Woodcrest", "Clovertown" and the upcoming "Tigerton" core CPUs for servers and workstations are also based on Core architecture, they are marketed under the Xeon brand. The first Core 2 Duo processors were fabricated on 300 mm wafers using a 65 nm manufacturing process.
Unlike the NetBurst architecture of Pentium 4 or Pentium D branded processors, the Core architecture does not stress extremely high clock speeds, but rather improvements in the processor's usage of both available clock cycles and power. This translated into more efficient decoding stages, execution units, caches, and buses, etc, reducing the Core 2 CPU's power consumption, while enhancing their processing capacity. With a TDP of up to only 65 W, the Core 2 dual-core Conroe consumed only half the power of some of the higher end dual-core Pentium D branded desktop chips with a TDP of up to 130 W (a high TDP requires many noisy cooling fans or a more expensive noiseless cooling system) and was more capable compared to them.
Intel Core 2 processors featured Intel 64 (also known as EM64T), Virtualization Technology (except T5500 or lower end E4x00), Execute Disable Bit, and SSE3. Core 2 also introduced SSSE3, Trusted Execution Technology, Enhanced SpeedStep, and Active Management Technology (iAMT2).
Typically for CPUs, the Core 2 Duo E4000/E6000, Core 2 Quad Q6600, Core 2 Extreme X6800, QX6700 and QX6800 CPUs were affected by bugs, but apparently minor.
Current processor cores
Conroe
The first Intel Core 2 Duo processor cores, code-named Conroe and given the Intel product code 80557, were launched on July 27, 2006 at Fragapalooza, a yearly gaming event in Edmonton, Alberta, Canada. These processors are built on a 65 nm process and are intended for desktops, replacing the Pentium 4 and Pentium D. Intel has claimed that Conroe provides 40% more performance at 40% less power compared to the Pentium D. All Conroe processors are manufactured with 4 MiB L2 cache; however, for marketing purposes, the E6300 and E6400 versions based on this core have half their cache disabled, leaving them with only 2 MiB of usable L2 cache.
The lower end E6300 (1.86 GHz) and E6400 (2.13 GHz), both with a 1066 MT/s FSB, were released on July 27, 2006. Traditionally, CPUs of the same family with less cache simply have the unavailable cache disabled, since this allows parts that fail quality control to be sold at a lower rating. As yields improve, they may be replaced with versions that only have the cache amount needed on the die, to bring down manufacturing cost. At launch time, Intel's prices for the Core 2 Duo E6300 and E6400 processors were US$183 and US$224 each in quantities of 1000. Conroe CPUs have improved capabilities over previous models with similar processor speeds. According to reviews, the larger 4 MiB L2 cache vs. the smaller 2 MiB L2 cache at the same frequency and FSB can provide a 0–9% performance gain with certain applications and 0–16% performance gain with certain games.The higher end Conroe processors are labeled as the E6600 and E6700 Core 2 Duo models, with the E6600 clocked at 2.4 GHz and the E6700 clocked at 2.67 GHz. The family has a 1066 MT/s front side bus, 4 MiB shared L2 cache, and 65 watts TDP. These processors have been tested against AMD's current top performing processors (Athlon 64 FX Series), which were, until this latest Intel release, the fastest CPUs available. Conroe chips also experience much lower heat output compared to their predecessors — a benefit of the new 65nm technology. At launch time, Intel's prices for the Core 2 Duo E6600 and E6700 processors were US$316 and US$530, respectively, each in quantities of 1000.
E6320 and E6420 Conroe CPUs at 1.86 and 2.13 GHz respectively were launched on April 22, 2007 featuring a full 4 MiB of cache and are considered Conroes.
Intel released four additional Core 2 Duo Processors on July 22nd, 2007. The release coincided with that of the Intel Bearlake (x3x) chipsets. The new processors are named Core 2 Duo E6540, E6550, E6750, and E6850. Processors with a number ending in "50" have a 1333 MT/s FSB. The processors all have 4 MiB of L2 cache. Their clock frequency is similar to that of the already released processors with the same first two digits (E6600, E6700, X6800). An additional model, the E6540, was launched with specifications similar to the E6550 but lacking Intel Trusted Execution Technology and vPro support. These processors are slated to compete with AMD's Stars processor line and are therefore priced below corresponding processors with a 1066 MT/s FSB.
Conroe XE
The Core 2 Extreme was officially released on July 29, 2006. However some retailers appeared to have released it on July 13, 2006, though at a higher premium. The less powerful E6x00 models of Core 2 Duo were scheduled for simultaneous release with the X6800, which are both available at this time. It is powered by the Conroe XE core and replaces the dual-core Pentium Extreme Edition processors. Core 2 Extreme has a clock speed of 2.93 GHz and a 1066 MT/s FSB, although it was initially expected to be released with a 3.33 GHz and 1333 MT/s. The TDP for this family is 75–80 watts. At full load the X6800 does not exceed 45 °C (113 °F), and with SpeedStep enabled the average temperature of the CPU when idle is essentially that of the ambient atmosphere.
At launch time, Intel's price for the Core 2 Extreme X6800 was US$999 each in quantities of 1000. Like the desktop Core 2 Duo, it has 4 MiB of shared L2 cache available. This means that the only major difference between the regular Core 2 Duo and Core 2 Extreme is the clock speed and unlocked multiplier, usual advantages of the "Extreme Edition." The unlocked upward multiplier is of use to enthusiasts which allow the user to set the clockspeed higher than shipping frequency without modifying the FSB unlike mainstream Core 2 Duo models which are downward unlocked only.
Allendale
There was contention as to whether the previously-available low-end Core 2 Duo desktop processors (E6300, at 1.86 GHz and E6400, at 2.13 GHz, both with 2 MiB L2 cache) are specimens of the Allendale core. Prior to Q1 2007, all E6300 and E6400 processors released were Conroe (4 MiB L2 cache) cores with half their L2 cache disabled. The Allendale core, manufactured with 2 MiB L2 cache in total, offers a smaller die size and therefore greater yields.
Quoted from The Tech Report:
You'll find plenty of sources that will tell you the code name for these 2MB Core 2 Duo processors is "Allendale," but Intel says otherwise. These CPUs are still code-named "Conroe," which makes sense since they're the same physical chips with half of their L2 cache disabled. Intel may well be cooking up a chip code-named Allendale with 2MB of L2 cache natively, but this is not that chip.
Another difference between the premium E6000 series (Conroe core) or (Allendale core) and the E4000 series (Allendale core) is the front side bus clock rating. The E4000 series are rated to run on a quad-pumped 200 MHz front side bus ("800 MT/s") while the E6000 series are rated to run on a quad-pumped 266 MHz front side bus ("1066 MT/s"). The E4000 series also lack support for Intel VT-x instructions.
The currently available Core 2 Duo E4300 only uses an Allendale core, released on January 21, 2007. The Allendale processors use a smaller mask with only 2 MiB of cache, thereby increasing the number of chips per wafer. Allendale processors are produced in the LGA775 form factor, on the 65 nm process node. It is unclear and a matter of contention whether the E6300 and E6400 models are still Conroe processors with half their L2 cache disabled or Allendale processors. It is possible that the E6300 and E6400 models can be both Allendale and Conroe, differentiated by the L2 and B2 steppings respectively.
Initial list price per processor in quantities of one thousand for the E4300 was US$163. A standard OEM price was US$175, or US$189 for a retail package. Price cuts were enacted on April 22, 2007, when the E4400 was released at $133 and the E4300 dropped to $113. Allendale processors with half their L2 cache disabled were released in mid-June 2007 under the Pentium Dual-Core brand name.
On July 22nd, 2007, an E4500 Allendale was launched, phasing out the E4300 model. This was accompanied by a price cut for the E4400 model.
Merom
Merom, the first mobile version of the Core 2, was officially released on July 27, 2006 but quietly began shipping to PC manufacturers in mid-July alongside Conroe.Merom is Intel's premier line of mobile processors, with largely the same features as Conroe, but with more emphasis on low power consumption to enhance notebook battery life. Merom-based Core 2 Duo provides 20% more performance yet maintains the same battery life as the Yonah-based Core Duo. Merom is the first Intel mobile processor to feature Intel 64 architecture.
The first version of Merom is "drop-in" compatible with Napa platform for Core Duo, requiring at most a motherboard BIOS update. It has a similar thermal envelope of 34 W and the same 667 MT/s FSB rate. Merom features 4 MiB L2 cache (budget T5xxx models have only 2 MiB L2 cache).
A second wave of Merom processors featuring an 800 MT/s FSB and using the new Socket P was launched on May 9, 2007. These chips are part of Santa Rosa platform. Low voltage versions were also released on May 9, 2007.
Merom (מרום) is the Hebrew word for a higher plane of existence or a level of heaven, BaMerom (במרום) means "in the heavens". The name was chosen by the Intel team in Haifa, Israel, who designed this processor.
See the Merom section of "List of Intel Core 2 microprocessors" for a list of Merom processors.
Kentsfield
The Kentsfield was the first Intel desktop quad core CPU branded as Core 2 (and Xeon for lower-end servers and workstations). The top-of-the-line Kentsfields were Core 2 Extreme models numbered QX6xx0, while the mainstream ones branded Core 2 Quad were numbered Q6xx0. All of them featured two 4 MB L2 caches. The mainstream Core 2 Quad Q6600, clocked at 2.4 GHz, was launched on January 8, 2007 at US$851 (reduced to US$530 on April 7, 2007, and to US$266 on July 22, 2007). July 22, 2007 marked the release of the next Core 2: Quad Q6700 and Extreme QX6850 Kentsfields at US$530 and US$999 respectively, and also price reduction of Core 2: Quad Q6600 and Extreme QX6800 Kentsfields to US$266 and US$999 respectively.
Kentsfield, like the Pentium D Presler, comprised two separate silicon dies. Each of Kentsfield's two dies was dual-core with the Core architecture, as did each die constituting alone every Core 2's dual-core only CPU. Hence, the max. power consumption (TDP) of the Kensfield (QX6800 - 130 watts, QX6700 - 130 W[19], Q6600 - 95 W[20]) was approx. double of its similarly clocked Core 2 Duo counterpart. For example, the QX6700 consisted of two E6700 chips connected together by a 1066 MT/s FSB on one MCM, resulting in lower costs but less bandwidth to the northbridge. The Kentsfield was one socket processor sitting in a LGA775 socket, as well as Core 2 Duo (AMD Quad FX consisted of two dual-core processors in two separate sockets on one motherboard with a 2 x 125 W= 250 W TDP).
A quad-core CPU, like the Kentsfield, processes very well with multi-threaded applications (typical for video editing, ray-tracing, or rendering), where its processing ability may approach double that of each of its halves comprising the equally clocked dual-core CPU. Similarly, Pentium D Presler had two dice in one package. A two-die CPU, however, can rarely double the processing ability of each of its constituent halves (e.g. the Kentsfield rarely doubles the ability of the Conroe), due to a loss of performance resulting from connecting them (i.e. sharing the narrow memory bandwidth, and operating system overhead of handling twice as many cores and threads).
Single or dual-threaded applications alone, including most games, do not benefit from the second pair of cores of a quad-core CPU over an equally clocked dual-core CPU. For example, with no increase in FSB speed and a mild reduction in processor frequency of the quad-core Extreme QX6700 over the older dual-core Extreme X6800, overall performance of the Kentsfield (QX6700) for those applications does not improve. Nevertheless, the simultaneous use of several processor-intensive single/dual-threaded applications on a quad-core CPU will generally lead to a dramatic overall performance increase over an equally clocked dual-core CPU. A quad-core CPU is useful also to run the both client and server processes of a game without noticeable lag in either thread, as each instance (up to four) could be running on a different core.
Kentsfield XE
The first Kentsfield, named Core 2 Extreme QX6700 (product code 80562) and clocked at 2.67 GHz, was released on November 2, 2006 at US$999. It was the first x86 quad-core processor ever, featured the Kentsfield XE core, and complemented the Core 2 Extreme X6800 dual-core processor based on the Conroe XE core. The CPUs with the Kentsfield XE core had the highest and unlocked multipliers like their Extreme predecessors. On April 8, 2007, a new top Kentsfield XE - the Core 2 Extreme QX6800 - was released within the 135 W TDP thermal envelope, and clocked at 2.93 GHz. It went to high end OEM-only systems at US$1,199.. On July 22, 2007, the new champ Core 2 Extreme QX6850 arrived, clocked at 3.0 GHz, with a faster 1.33 GHz FSB, and at US$999 - a typical price for a top Kentsfield XE CPU.
The formerly available Core 2 Extreme QX6700 was relaunched on July 22nd, 2007 as the Core 2 Quad Q6700, clocked at 2.66 GHz, but it consumes less power than QX6700. The price of the Q6600 has been dropped to US$266 on July 22nd, 2007.
Merom XE
Merom XE is a laptop CPU designed for ultra-high end laptops. It will be released in two models, the X7900 and the X7800. These will feature an 800 MHz FSB. The X7800 will be clocked at 2.6 GHz and will cost around $795.The processor will feature a 44WT TDP and will require the new Intel Centrino (Santa Rosa) platform. The X7900 will be clocked at 2.8 GHz, but its cost is unknown, but expect it to be more than 1000 dollars per CPU in packs of 1000.
Penryn
The successor to the Merom core currently used for the Core 2 Duo T5000/T7000 series mobile processors, code-named Penryn, will debut the 45 nanometer process that will also be used for the Conroe sequel, Wolfdale (see below). Many details about Penryn appeared at the April 2007 Intel Developer Forum. Its successor is expected to be Nehalem.
Important advances include the addition of new instructions (including SSE4, also known as Penryn New Instructions) and new fabrication materials (most significantly a hafnium-based dielectric).
Penryn is intended to be paired with a new chipset, Bearlake, which will include an increase in bus speed (connection to the northbridge, etc.) for certain models to 1333 MT/s and will include support for DDR3 SDRAM; Intel believes that DDR3 is particularly useful in the power- and heat-constrained environments within mobile equipment.
Penryn will also be released in a quad-core version for desktop replacement notebooks.
Wolfdale and Yorkfield
Wolfdale will be the desktop version of Penryn, with two cores sharing 6 MiB of L2 cache and 1333 MHz FSB. Two Wolfdale dies on a single module will make up a Yorkfield chip, the successor to the Kentsfield processor. Each die will share 6 MiB L2 cache, for a total of 12 MiB, and this chip will also have a 1333 MHz FSB. These processors are expected to become available in late 2007 or early 2008, and the platform will support DDR3. At the Intel Developer Forum 2007 a Yorkfield processor was compared with a Kentsfield processor.
Even further, the latest known codenames for future processors (perhaps based on a new post-Core microarchitecture) are Nehalem and Sandy Bridge (formerly known as Gesher), and little is known about either of them. Nehalem will be a 45 nm process debuting in 2008, followed by a 32 nm shrink codenamed Westmere (Nehalem-C), and Sandy Bridge will be 32 nm with a new microarchitecture debuting in 2010, provided that Intel stays on target with its roadmap. n 2011, Intel will launch its first processor based on a 22 nm process. Based on Intel's cycle alternating new architectures and die shrinks every two years, it is currently assumed that this will be a shrink of Sandy Bridge.
System requirements
Motherboard compatibility
Conroe, Conroe XE and Allendale all use Socket LGA775; however, not every motherboard is compatible with these processors.
Supporting chipsets are:
Intel: 865PE/G/GV/G, 945P/PL/G/GZ/GC, P65P/G, 975X, P/G/Q965, Q963, 946GZ/PL; X3x, P3x, G3x, Q3x
NVIDIA: nForce4 Ultra/SLI X16 for Intel, nForce 570/590 SLI for Intel and nForce 650i Ultra/650i SLI/680i LT SLI/680i SLI.
VIA: P4M800, P4M800PRO, P4M890, P4M900, PT880 Pro/Ultra, PT890.
SiS: 662, 671, 671fx, 672, 672fx
ATI: Radeon Xpress 200 and CrossFire Xpress 3200 for Intel
Although a motherboard may have the required chipset to support Conroe, some motherboards based on the above mentioned chipsets do not support Conroe. This is because all Conroe-based processors require a new power delivery feature set specified in Voltage Regulator-Down (VRD) 11.0. This requirement is a result of Conroe's significantly lower power consumption, compared to the Pentium 4/D CPUs it is replacing. A motherboard that has both a supporting chipset and VRD 11 supports Conroe processors, but even then some boards will need an updated BIOS to recognize Conroe's FID (Frequency ID) and VID (Voltage ID).
DDR2 memory modules
Unlike the previous Pentium 4 and Pentium D design, the Core 2 technology sees a greater benefit from memory running synchronously with the Front Side Bus (FSB). This means that for the Conroe CPUs with FSB of 1066 MT/s, the ideal memory speed is PC2-4200. In some configurations, using PC2-5300 can actually decrease performance. Only when going to PC2-6400 is there a significant performance increase. While expensive DDR2 memory models with tighter timings do improve performance, the difference in real world games and applications is negligible.
Optimally, the memory bandwidth afforded should match the bandwidth of the FSB closely. The AGTL+ PSB used by all NetBurst processors as well as current and medium-term (pre-CSI) Core 2 processors provide a 64-bit data path. Current chipsets provide for two DDR or two DDR2 channels.
Matched processor and RAM ratings
Processor Model
DDR or DDR2 rating
Memory channels
Bandwidth
T5200
PC2-4200 (DDR2-533)
Single channel
4.267 GB/s
T5n00 and T7n00
PC2-5300 (DDR2-667)
Single channel
5.333 GB/s
Socket P T7n00
PC2-3200 (DDR2-400)
Dual channel
6.400 GB/s
PC2-6400 (DDR2-800)
Single channel
6.400 GB/s
E4n00/Pentium E21n0/Celeron 4n0
PC3200 (DDR400) or PC2-3200 (DDR2-400)
Dual channel
6.400 GB/s
PC2-6400 (DDR2-800)
Single channel
6.400 GB/s
E6n00, E6n20, X6n00, Q6n00 and QX6n00
PC2-4200 (DDR2-533)
Dual channel
8.533 GB/s
PC3-8500 (DDR3-1066)
Single channel
8.533 GB/s
E6n50
PC2-5300 (DDR2-667)
Dual channel
10.667 GB/s
PC3-10600 (DDR3-1333)
Single channel
10.667 GB/s
On jobs requiring large amounts of memory access, the quad-core Core 2 processors can benefit significantly from using a PC2-8500 memory, which runs exactly twice as fast as the FSB; this is not an officially supported configuration, but a number of motherboards offer it.
The Core 2 processor does not require the use of DDR2. While the Intel 975X and P965 chipsets require this memory, some motherboards and chipsets support both the Core 2 and DDR memory. When using DDR memory, performance may be reduced because of the lower available memory bandwidth.
Chip bugs
The Core 2 Memory management unit (MMU) does not operate as previously specified or implemented in previous generations of x86 hardware. This may cause problems, many of them serious security and stability issues, with existing operating system software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the Translation Lookaside Buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data.
Among the issues noted:
Write-protect or non-execute bit for a page table entry is ignored.
Floating point instruction non-coherencies.
Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.
Intel errata AI65, AI79, AI43, AI39, AI90, AI99 are said to be particulary serious.
Among those who have noted the errata to be particularly serious are OpenBSD's Theo de Raadt[2] and DragonFly BSD's Matthew Dillon[3]. Taking a contrasting view was Linus Torvalds, calling the issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better.
Pricing
The pricing for various models of Core 2, in lots of 1000 to OEMs, at the time the processors were released, can be found in the list of Intel Core 2 microprocessors. It should be noted that these prices are what it costs system builders such as Dell and HP to stock Core 2 processors. There are no set MSRPs for Core 2 CPUs in the retail channel — prices at retailers are usually very close to the aforementioned prices, but are dependent on what the supplier is charging to stock these CPUs as well as supply and demand.
Nomenclature and abbreviations
With the release of the new Core 2 processor, the abbreviation C2 has come into common use, as well variants C2D (the present Core 2 Duo), and C2Q, C2E to refer to the Core 2 Quad and Core 2 Extreme processors respectively. C2QX stands for the Extreme-Editions of the Quad (QX6700 or QX6800).

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Intel Core

By : http://en.wikipedia.org

Intel Core

CoreProduced:2006 -
Manufacturer:Intel
CPU Speeds:1.06 GHz to 2.33 GHz
FSB Speeds:533 MT/s to 667 MT/s
Process:(MOSFET channel length)0.065 µm
Instruction Set:x86
Microarchitecture:P6 (Pentium M) derivative
Socket:Socket M
Core Name:Yonah

The Core brand refers to Intel's 32-bit mobile dual-core x86 CPUs derived from the Pentium M branded processor's microarchitecture (an interim step between the Intel P6 and Core microarchitecture), which emerged in parallel with the NetBurst (Intel P68) microarchitecture of the Pentium 4 brand, and was a precursor of the 64-bit Core microarchitecture. The Core comprised two branches: the Duo (dual-core) and Solo (Duo with one disabled core), which replaced the Pentium M brand of single-core mobile processor.
The Core brand was launched on January 5, 2006 by the release of the 32-bit Yonah core CPU - Intel's first dual-core mobile (low-power) processor. Its dual-core closely resembled two interconnected Pentium M branded CPUs packaged, as a single die (piece) silicon chip (IC). Hence, the 32-bit microarchitecture of Core branded CPUs - contrary to its name - had more in common with Pentium M branded CPUs than with the following 64-bit Core microarchitecture of Core 2 branded CPUs. Despite a major rebranding effort by Intel starting January 2006, some computers with the Yonah core continued to be marked as Pentium M.
In 2007, Intel began branding the Yonah core CPUs as Pentium Dual-Core intended for lower-end mobile only computers, unlike the 64-bit Core microarchitecture CPUs branded as Intel Core 2 (for higher-end computers) and also as Pentium Dual-Core (for lower-end desktops only). In short, the Core brand refers to processors with the "mobile" derivative of 32-bit Intel P6 microarchitecture (preceding the Core microarchitecture), whereas the Intel Core 2 brand refers to CPUs with the 64-bit Core microarchitecture.
//
Yonah
Yonah was the code name for (the core of) Intel's first generation of 65 nm process mobile microprocessors, based on the Banias/Dothan-core Pentium M microarchitecture. SIMD performance has been improved through the addition of SSE3 instructions and improvements to SSE and SSE2 implementations, while integer performance decreased slightly due to higher latency cache. Additionally, Yonah includes support for the NX bit.
The Intel Core Duo brand refers to the world's first low-power (less than 25 watts) Yonah dual-core microprocessor, with the previous low being AMD's Opteron 260 and 860 HE at 55 watts. Core Duo was released on 5 January 2006, with the other components of the Napa platform. It was the first Intel processor to be used in Apple Macintosh products (although the Apple Developer Transition Kit machines, non-production units distributed to some developers, used Pentium 4 processors).[1]
Contrary to early reports, the Intel Core Duo supports Intel VT x86 virtualization technology, except in the T2300E model and proprietary T2050/T2150/T2250 mounted by OEMs (cf. the Intel Centrino Duo Mobile Technology Performance Brief and Intel's Processor Number Feature Table). The Intel Pentium Dual Core processors may or may not have this feature. However, it seems some vendors, like HP, have chosen to disable this feature,with others making it available through a BIOS option.
Intel 64 (Intel's x86-64 implementation) is not supported by Yonah. However, Intel 64 support is integrated in Yonah's successor, the mobile version of Core 2, code-named Merom.
Intel Core Duo (product code 80539) consists of two cores on one die, a 2 MiB L2 cache shared by both cores, and an arbiter bus that controls both L2 cache and FSB access. Upcoming steppings of Core Duo processors will also include the ability to disable one core to conserve power.
Intel Core Solo (product code 80538) uses the same two-core die as the Core Duo, but features only one active core. This allows Intel to sell dies that have a manufacturing defect in one but not both of the cores. Depending on demand, Intel may also simply disable one of the cores to sell the chip at the Core Solo price -- this requires less effort than launching and maintaining a separate line of CPUs that physically only have one core. Intel used the same strategy previously with the 486 CPU in which early 486SX CPUs were in fact manufactured as 486DX CPUs but the FPU failed quality control and the connection was physically severed.
Technical specifications
Core Duo contains 151 million transistors, including the shared 2 MiB L2 cache. Yonah's execution core contains a 12 stage pipeline, forecast to eventually be able to run at a maximum frequency of 2.33–2.50 GHz. The communication between the L2 cache and both execution cores is handled by an arbitration bus unit, which reduces cache coherency traffic over the FSB, at the expense of raising the core-to-L2 latency from 10 clock cycles (in the Dothan Pentium M) to 14 clock cycles. The increase in clock frequency offsets the impact of the increased clock cycle latency. The power management components of the core features improved grained thermal control, as well as independent scaling of power between the two cores, resulting in very efficient management of power.
Core processors communicate with the system chipset over a 667 MT/s front side bus (FSB), up from 533 MT/s used by the fastest Pentium M. New T2050 & T2250 have also appeared in OEM systems as a low-cost option with a lower 533 MHz FSB and no Virtualization Technology. No official data on these processors is yet available from Intel.
Yonah is supported by the 945GM, 945PM, 945GT, 965GM, 965PM, and 965GT system chipsets. Core Duo and Core Solo use Socket M, but due to pin arrangement and new chipset functions are not compatible with any previous Pentium M motherboard.
The T2300E was later introduced as a replacement for the T2300. It has dropped support for Virtualization Technology. Early Intel specifications mistakenly claimed a halving of the Thermal Design Power.
Advantages and shortcomings
The Duo version of Intel Core (Yonah) includes two computational cores, providing performance per watt almost as good as any previous single core Intel processors. In battery-operated devices such as notebook computers, this translates to getting as much total work done per battery charge as with older computers, although the same total work may be done faster. When parallel computations and multiprocessing are able to utilize both cores, the Intel Core Duo delivers much higher peak speed compared to the single-core chips previously available for mobile devices.
The shortcomings of Intel Core (Yonah) are:
The same or even slightly worse "performance per watt" in single threaded or non-parallel applications compared to its predecessor.
32-bit processes only. 64-bit processes are not supported. (See the Intel Core 2 successor, which is a 64-bit processor.)
High memory latency due to the lack of on-die memory controller (further aggravated by system-chipset's use of DDR-II RAM)
Limited Floating Point Unit (multiply/divide) throughput for non-parallel computations or single-threaded processes; this is due to the smaller number of floating-point units in each CPU core compared to some previous designs.
The Yonah platform requires all main-memory transactions to pass through the Northbridge of the chipset, increasing latency compared to the AMD's Turion platform. (Intel's Non-Core2 Based Pentium processors have this same performance bottleneck.) However, application tests showed Intel Core's L2-cache system is quite effective at overcoming main-memory latency; despite this limitation, Intel Core (Yonah) sometimes managed to outperform AMD's Turion.
The Sossaman processor for servers, which is based on Yonah, also lacks Intel 64-bit support. For the server market, this had more severe consequences, since all major server operating systems already supported x86-64, and Microsoft Exchange Server 2007 even requires a 64-bit processor to run.
According to Mobile Roadmaps from 2005, Intel's Yonah project originally focused more on reducing the power consumption of its p6+ Pentium M-based processor and aimed to reduce it by 50% for Intel Core (Yonah). Intel continued recommending Pentium NetBurst-based processors for mobile high performance applications (although these were less power efficient) until the Yonah project succeeded in extracting higher performance from its lower-power-consumption design. The Intel Core Duo's inclusion of two highly-efficient cores on one chip can provide better performance than a Pentium NetBurst core, but with much better power-efficiency. Intel no longer recommends its Pentium Netburst-based processors for mobile devices.
On July 27, 2006, Intel's Core 2 processors were released. By 2Q 2007, Intel expected 90% of its laptop CPU production to be converted to the heavily-revised Intel Core 2 processors. The original Intel Core (Yonah) product had an unusually short lifespan as a stepping stone to the 64-bit Intel Core 2.
Non-Core Yonah variants
There were two variants and one derivative of the Yonah, which did not bear the "Intel Core" brand name. A dual-core (server) derivative, code-named Sossaman, was released on 14 March 2006 as the Xeon (branded) LV (low-voltage). The Sossaman differed from the Yonah only in its support for dual-socket configurations (two CPUs - i.e. four cores - on board, like AMD Quad FX), and implementation of 36-bit memory addressing (PAE mode). A single-core variant, code-named Yonah-1024, was released as the Celeron (branded) M 400 series CPUs. It was largely identical to the Core Solo branded Yonah, except that it only had half the L2 cache and did not support SpeedStep. Another dual-core variant of the Core Duo branded Yonah was released as the Intel Pentium Dual-Core branded T2060, T2080, and T2130 mobile CPUs.
The successor to Core is the mobile version of the Intel Core 2 line of processors using cores based upon the Intel Core microarchitecture, released on July 27, 2006. The release of the mobile version of Intel Core 2 marks the reunification of Intel's desktop and mobile product lines as Core 2 processors were released for desktops and notebooks, unlike the first Intel Core CPUs that were targeted only for notebooks (although some small form factor and all-in-one desktops, like the iMac, also used Core processors).
Unlike the Intel Core, Intel Core 2 is a 64-bit processor, supporting Intel 64. Another difference between the original Core Duo and the new Core 2 Duo is an increase in the amount of Level 2 cache. The new Core 2 Duo has doubled the amount of on-board cache to 4 MiB. Both chips have a 65 nm process technology architecture and support a 667-1333 MHz front-side-bus (FSB).

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