Cloned Motherboards

by : http://www.hardwaresecrets.com/article/65/1

Cloned Motherboards

There are several motherboards that are not manufactured, rather they are bought from another manufacturer and have their tag sticked to them, as it happens to those from Amptron, Alton, Aristo and Matsonic. Matsonic used to sell their board under the brand "Eurone. All those "manufacturers" buy boards from ECS (EliteGroup Systems), which is one of the largest motherboard manufacturers in the world and is also the owner of the brand PCChips, one of the most popular motherboard manufacturer in developing countries because of their low prices.

ECS says they use the brand PCChips for their boards for the low-end PC market, while the boards sold under the brand ECS have better quality control. However, several ECS and PCChips motherboards are simply identical.

For example, if you buy an ECS K7SOM+ motherboard in the belief you are making a better deal than buying one from PCChips you are mistaken, for that motherboard is actually the M810DLU from PCChips. Similarly, if you an MS9138E from Matsonic you will be really taking home an M925 from PCChips.

We compiled two tables showing the correspondence of the most popular cloned motherboards on the market today. Notice that that table is far from being thorough, being just a fast guide to be used when buying a low cost motherboard.

Socket 478 (Intel Processors)

ECS	PCChips	Matsonic	Amptron	Chipset
P4IBASD V3.X	M902LU v3.0	MS9047C		Intel 845D
P4S5A	M930LMR			SiS 645
P4S5A/DX	M930ALU v5.x			SiS 645DX
P4S5MG/651+	M935ALU v5.1B			SiS 651
P4S5MG/GL	M935LU v5.1B (M935DELR)			SiS 650GL
P4S5MG/GL+	M935MLU5			SiS 650GL
P4S8AG	M947			SiS 648
P4VMM2		MS9138D		VIA P4M266
P4VMM2 v3.1	M925 ALMU (M925LU v3.x)	MS9138E	XP4-925ALU	VIA P4M266
P4VXAS2 v2.X		MS9107C		VIA P4X266A
P4VXASD2 v5.X	M922 v5.0			VIA P4X333
P4VXASD2+	M922LU v5.0	MS9147C	XP4-922LU	VIA P4X333

Socket A (AMD Processors)

ECS	PCChips	Matsonic	Amptron	Chipset
	M825LU v3.x		K7-825LU v.3.1	VIA KM266
K7S7AG	M847			SiS 746
K7SEM v3.0	M810L v7.1C		K7-810CLM4	SiS 730S
K7SOM+	M810DLU		K7-810DLM4	SiS 730D
K7VMM	M825LMU			VIA KM266
K7VTA3 V2.X		MS8137C+		KT266A
K7VTA3 V7.0		MS8167C		KT333CF

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Athlon 64

by :www.hardwaresecrets.com/article/272

Athlon 64

In this tutorial we will list all Athlon 64, Athlon 64 FX and Athlon 64 X2 CPU models from AMD released to date and the main differences between them.
By the way, AMD has recently changed the name of those CPUs, dropping the number "64" from their name. So Athlon X2 and Athlon 64 X2 are the same CPU, and so on.
Those three CPUs are based on AMD64 architecture, where the main feature is the memory controller embedded in the processor itself and not located on the chipset like all other CPUs. Besides Athlon 64, Athlon 64 FX and Athlon 64 X2 we also have Sempron (models based on sockets 754 and AM2), Opteron and Turion 64 CPUs based on this architecture. Read our Inside AMD64 Architecture for an in-depth explanation on how these CPUs work.
Because of this architecture the communication between the CPU and the memory modules is done thru a dedicated memory bus, while the communication between the CPU and the chipset uses a separated bus, HyperTransport (click here to read our tutorial on HyperTransport).
AMD CPUs based on Athlon 64 architecture can be found with the following socket types:
Socket 754: Used by early Athlon 64, some Sempron models and Turion 64. Their memory controller is single channel, meaning that the CPU accesses memory at 64-bit rate.
Socket 939: Used by Athlon 64, Athlon 64 FX , Athlon 64 X2 and Opteron processors. Their memory controller is dual channel, meaning that the CPU accesses memory at 128-bit rate, if two memory modules are used.
Socket 940: Used by early Athlon 64 FX and Opteron processors. Their memory controller is dual channel, meaning that the CPU accesses memory at 128-bit rate, if two memory modules (or an even number of memory modules) are used. They require ECC memory type.
Socket AM2: Used by Athlon 64, Athlon 64 FX, Athlon 64 X2 and Sempron (some models) processors. On these models the embedded memory controller supports DDR2-533, DDR2-667 and DDR2-800 memories at dual channel configuration, meaning that the CPU accesses the memory at 128-bit rate if two modules (or an even number of memory modules) are used. Keep in mind that the memory controller of socket 754, 939 and 940 CPUs support only DDR memories.
Socket F: This 1,207-pin socket created for the latest Opteron models is also used by the Athlon 64 FX processors used on AMD’s Quad FX platform (Athlon 64 FX models 7x). CPUs based on this socket can operate under SMP (Symmetric Multiprocessing) mode, i.e. you can have more than one CPU working in parallel. Like socket AM2 processors, the memory controller found on socket F processors supports DDR2-533, DDR2-667 and DDR2-800 memories under dual channel configuration, meaning that the CPU can access the memory at a 128-bit rate if an even number of memory modules is used.
The memory controller integrated on socket AM2 and socket F CPUs can support DDR2-533, DDR2-667 and DDR2-800 memories. The problem, however, is how the memory bus clock is achieved. Instead of being generated thru the CPU base clock (HTT clock, which is of 200 MHz), it divides the CPU internal clock. The value of this divider is half the value of the CPU multiplier.
For example, an AMD64 CPU with a clock multiplier of 12x will have a memory bus divider of 6. So this CPU will work at 2.4 GHz (200 MHz x 12) and its memories will work at 400 MHz (DDR2-800, 2,400 MHz / 6). Keep in mind that DDR and DDR2 memories are rated with double their real clock rate.
The problem is when the CPU clock multiplier is an odd number. For an AM2 CPU with a clock multiplier of 13x, theoretically its memory bus divider would be of 6.5. Since the AMD64 memory bus doesn’t work with “broken” dividers, it is rounded up to the next higher number, seven in this case. So while this CPU will work at 2.6 GHz (200 MHz x 13), its memory bus will work at 371 MHz (742 MHz DDR) and not at 400 MHz (800 MHz DDR), making the CPU to not achieve the maximum bandwidth the DDR2 memory can provide.

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Installing Frontal USB Ports

By : www.hardwaresecrets.com/article/90

Installing Frontal USB Ports

The most sophisticated cases have frontal USB ports. To use them, you need to connect them to the motherboard of your computer. In this tutorial we will show how this connection must be done.






Figure 1: Detail of a case with two USB ports on its front (this case has also two jacks from on-board audio).
Nowadays motherboards have four, six or eight USB ports, but normally only two or four of them are directly soldered to the motherboard, at its back. Due to that, we generally two USB ports left in the motherboard. These left ports are usually available in 9- or 10-pin connector, as you can see on Figures 2 and 3. It is in that connector that the USB ports of the front panel of the case should be installed.






Figure 2: 9-pin USB header on the motherboard where the frontal USB ports should be installed.






Figure 3: Another example of the 9-pin USB header where the frontal USB ports should be installed. In this case, where we have two connectors available, just one will be used.






The biggest problem is that there is no standardization among the several motherboards manufacturers for the functions of each pin, that is, pin 1 of a motherboard connector may have a different meaning from pin 1 of a motherboard connector from another manufacturer. Because of that, each wire of the USB ports of the front panel of the case use individual connectors. As each USB port uses four wires, your case will have eight wires coming from the front panel, in case your case has two USB ports, which is the most common number.






Figure 4: Wires from the frontal USB ports of the case.
On each wire connector you can read its meaning, which may be +5V (or VCC or Power), D+, D - and GND. Besides the meaning, in each connector you can read whether the wire belongs to port 1 (or A or X) or to port 2 (or B or Y) of the case. The first step for the installation is to separate the wires according to the port, that is, to separate the wires in two groups: port 1 and port 2.


Next you must install the wires in the motherboard connector. The biggest problem is to know the meaning of each motherboard pin, since this is usually not written on the motherboard. For this task, you will need to check the board manual. There you will find the meaning of each connector pin, as we show on Figure 6. All you have to do is to install each of the wires (+5V, D+, D - and GND) in the correct places as shown in the manual. In the motherboard of our example, the port 1 wires must be connected the following way: +5V to pin 1, D- to pin 3, D+ to pin 5, and GND to pin 7. The port 2 wires must be connected the following way: +5V to pin 2, D- to pin 4, D+ to pin 6, and GND to pin 8. Notice that the meaning of each pin of your motherboard may be different from this example, therefore you will need to check your board manual. Usually the wires of a door will be one side of the connector (odd pins) and the wires of the other port will be on the other side (even pins).






Figure 6: USB header pin-out, from the motherboard manual.

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PC Assembling Problems

By :www.hardwaresecrets.com/article/42

Preventing Overheating

If you want to ensure that you won’t face overheating, random crashes (resets and the infamous “Blue Screen of Death”) and performance issues with your PC you should check whether it is assembled 100% correctly or not. In this tutorial we will show you where to look for assembling errors on your PC.
First, let’s start with the PC assembly itself. The errors describe on this page can overheat your PC thus causing random problems like random resets and crashes (PC “freezing”, “Blue Screen of Death”, etc).
Antistatic foam: Most motherboards come from factory with an antistatic foam (usually pink, white or black) in their packing. Many technicians, when installing the motherboard to the case, pinch this foam between motherboard and metallic chassis, thinking that this procedure will avoid that motherboard from touching the case metallic frame. It happens that this foam holds motherboard-generated heat, hindering the normal airflow that exists between motherboard and the case chassis. Therefore, it is quite common that a computer assembled using this foam crashes or issues random errors, due to the overheating.
Internal main power cord: In AT cases it is quite common to have the main power cord that connects the power supply to the power-on switch in front panel hanging loose over motherboard, often hindering the heat dissipation and even contacting the processor fan, causing it to stop running and PC to crash due to overheating. The ideal would be to lay this cable to the power supply switch by the right side of the case (facing front of case in upright position), in the upper part of the frame, and not hanging loose by left side, as it is common to find. Since AT cases are used only on very old PCs, you probably won’t face this issue, however we kept it listed here for historic purposes.

Other loose cables: The same idea applies to all other cables inside the PC, like the power supply cables and the flat cables used to connect the hard disk drives, optical drives and floppy disk drives. You should fasten these cables with a cable holder and put them inside an empty 5 ¼” bay in order to prevent these cables from blocking the airflow inside the PC and also preventing them to stuck the CPU fan.

Thermal grease: If you are facing overheating problems with your CPU, you should check whether thermal grease was correctly applied on the CPU or not.

Under dimensioned case: Cases look all the same, but they aren’t. Current Intel CPUs (Pentium 4 “Prescott” and beyond) require cases with a side duct in order to improve the airflow inside the case. If you don’t use a case with this side duct you may face overheating problems.

Extra fans wrongly installed: If your case has extra fans, you should check if they are installed on the right position, i.e. blowing the air in the right direction. Fans installed on the rear part of the case must be installed pulling the hot air from inside the PC case to the outside. Fans installed on the front part of the case must be installed pushing cold air from outside the case to the inside. Putting your hand near the fan should be enough for you to feel which way it is blowing air. If any extra fan is reversed, just remove it from your case and install it again, flipping it over.
The problems listed below are not directly related to overheating, but you should check them as well.
Loose motherboard: Your motherboard must be very well fastened to case's metallic frame. We've seen many cases where the computer gives random resets or crashes when the desk was rocked, just because the motherboard was practically loose inside the case. In other cases, it is very common for the PC to lose its machine setup when a new daughter board is installed, as motherboard bends (due to lack of padding points) and some of the motherboard soldering points contact the metallic frame. Therefore your motherboard must be very well fastened to case's frame, using the largest quantity of fastening points as possible.
Hard disk flat cable: If you still use a parallel IDE hard disk drive (e.g. ATA-100, ATA-133) instead of Serial ATA (SATA), you should check carefully how it is installed. Parallel IDE hard disk drives use a 40- or 80-wire flat cable that normally has three connectors, one in each cable end and one midway. The hard disk must be connected to one end of the cable and motherboard to the other end. The midway connector stays normally loose. It happens that some technicians connect the hard disk to the midway connector, is such a way that a cable end connector hangs loose. This is not good, as this stretch of the cable will actuate as an antenna, receiving and injecting noise in the data transmission, and as such hard disk transfer rate will be reduced. Also, if your hard disk cable is using a 40-wire flat cable, we recommend you to replace it with an 80-wire cable
Optical drive as hard disk slave: Also if you still use a parallel IDE hard disk drive, the optical drive (CD, DVD, etc) must be installed in the secondary IDE port of motherboard, configured as "master". Many people install the optical drive on the same cable as hard disk (using that midway connector that stays usually empty), as "slave". In that way the hard disk drive and the optical drive will have to strive for cable utilization, as they use same cable, and both devices can't change information with the system processor simultaneously, reducing computer performance. If your computer optical drive is sharing the same cable as the hard disk drive, undo this installation: install it on the motherboard secondary IDE port as “master” (you will need a 40- or 80-wire flat cable). Newer motherboards, however, are coming with just one parallel IDE port (see Figure 11), giving us no other option than installing the optical drive and the hard disk drive on the same cable. If this is your case, we highly recommend you to replace your hard disk drive with a Serial ATA one in order to leave the optical unit alone on the parallel IDE port, thus increasing system disk performance.

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Next Pentium 4

http://www.hardwareanalysis.com/content/article/1686/

By: Dan Mepham

The next Pentium 4 processor, Prescott arrives

In 1965, just a few years after the first integrated circuits saw the light of day, a chemist by the name of Dr. Gordon Moore made an observation that would become a guiding rule for the next forty years. His prediction, affectionately dubbed 'Moore's Law' by the press, stated that the speed and number of transistors built into the latest integrated circuits would double every eighteen months. Three years later, in 1968, Moore would go on to co-found what is now the world’s largest semiconductor manufacturer, and would have a first-hand role in ensuring that his prediction would hold. And hold it has. Intel’s first processors in the early 1970’s consisted of just one or two thousand transistors. That increased to tens of thousands in the late seventies as Intel pushed its 8086 processor. Progress continued through the hundreds of thousands of transistors with the 80286 and 80386 families, and finally reached the million transistor mark with the 486DX and its integrated FPU. The nineties was the decade of the Pentium processor, from its 3-million transistor introduction in 1993 to the 25-million transistor Pentium III in the late nineties. Finally, the current Pentium 4 processors boast a modest 55-million transistor count. Key to increasing transistor count, and therefore performance, is the reduction of the size of those transistors. 55 million transistors as they were in 1970 would never have worked; the circuit would have been too huge and too hot to be practical. Decreasing the size of the transistors allows them to be made cheaper, switched faster, and run cooler. Over the decades we’ve seen transistors drop from several microns down to the current 0.13 micron technology.Today we see the introduction of Intel’s smallest mass-produced transistor at just 0.09 microns (90 nanometers). Welcome, ladies and gentlemen, to Prescott Country.
Caching In
The use of the 90nm transistor allows Intel to construct much larger (in terms of the number of transistors) processors, while keeping the physical size small. When processors are manufactured, the yield rates on those processors are directly related to how large, physically, the processors are. A processor that is twice the size of another is essentially twice as likely to contain manufacturing impurities, and therefore will be subject to much lower yield rates. We’ve seen this on a simple basis with respect to Intel’s server products. Later versions of the Pentium III Xeon, for example, incorporated huge on-die caches that bumped the transistor count into the hundreds of millions, and resulted in a die size two to three times the size of a typical desktop processor at the time. These huge Xeons were difficult to manufacture, and came with a corresponding price premium. The move to 90nm technology has allowed Intel to cram a comparatively huge amount of cache memory onto the Pentium 4 die. Prescott improves on the previous Northwood processor by boasting a huge 1MB L2 cache. Despite the larger cache, which helps to drive Prescott’s transistor count to over 125 million, the processor’s physical size remains manageable at only 112 square millimeters – roughly 50% smaller than Intel’s first Willamette Pentium 4 with its tiny 256kB L2 cache.In addition, Intel has also taken the opportunity to increase the size of the Pentium 4’s L1 cache as well. Prescott’s L1 data cache is now doubled to 16kB, while the L1 instruction cache (or Execution Trace Cache) remains at 12k micro-ops. The Pentium 4 was initially designed with a small 8kB L1 data cache as a tradeoff in order to maximize the speed of the cache. Set-associativity of the L1 data cache has also increased from 4-way to 8-way.

Figs. 1 & 2 - Color-enhanced photos of Intel's Pentium 4 processor dies. On the left is the 130nm Northwood core; the 90nm Prescott core is on the right. Notice the larger L2 area on the Prescott die.

As you'll see later in the benchmarks, however, there are tradeoffs necessary in order to implement such a large cache.

Branching Off
Intel has further made some subtle but important enhancements to the Pentium 4’s branch prediction systems. Mispredicted code branches result in pipeline stalls as the entire pipeline needs to be flushed to clear the bad branch. With the Pentium 4’s extremely deep pipeline (more on this later), stalls have a dramatic impact on performance.Despite the exemplary accuracy of the Pentium 4’s branch predictor units, there nevertheless exist situations in which the BPU simply cannot make a prediction. In this case, the Branch Target Buffer (BTB) contains no prediction information about the current branch, and so the processor defaults to a rather simple, static prediction algorithm. Intel has enhanced this simple static algorithm to be more accurate. Without excessive description, the new prediction algorithm examines the distance and other properties of the branch to attempt to ascertain whether the branch may be a loop-ending command, and thus whether or not it should be taken. Subtle enhancements have also been made to the dynamic brand prediction algorithms as well.Branch prediction success rate is often difficult to quantify, and changes to branch prediction schemes can show various outcomes, ranging from much better performance, to marginally better performance, or even to decreased performance in some situations. We have been given access to some in-house testing conducted by Intel, and while we cannot post actual numbers at this time, we can summarize the results as follows: Testing using the SPECint_base2000 software showed that Prescott’s mispredicted branch rate ranged from 54% lower to 10% higher than Northwood’s at the extremes, and the overall average branch misprediction rate was about 12% lower on the new Prescott core than Northwood; an impressive improvement.Again, these results are difficult to quantify in terms of real-world performance, but the effects should not be underestimated given the degree to which mispredicted branches impact the performance of Prescott’s deep pipeline.

Round 3, SSE Gets a Refresh
Prescott marks the introduction of Intel’s latest extensions to the IA-32 ISA, adding thirteen new instructions. Most of these new instructions make use of the Streaming SIMD Extension (SSE) registers, and as a result, Intel has named the new instructions SSE3. The majority of these instructions relate to graphics and complex arithmetic operations. Two of the instructions were designed to help software make better use of the processor’s Hyper-Threading capability by helping to indicate when a thread may no longer be engaged in useful work.Naturally the benefits of these added instructions will not become apparent until software developers begin to make use of them. As is generally the case with instruction set extensions, there will be particular pieces of software or particular operations that exhibit very tangible performance improvements, while others really have no use for the added instructions, and thus show no change.

Intel's 2004 Roadmap, Sock-et to Me!
Both Prescott and Northwood are introduced in 3.40 GHz versions today, and both are packaged in the current Socket-478 platform. 3.40 GHz will be the final stop for the Socket-478 platform at the high-end, however.When Intel introduces a 3.60 GHz variant of the Prescott processor in Q2 2004, it will be on the new Socket-775 platform only. Socket-775 boards will have much tougher power design specifications that will be necessary to feed these thirsty processors at 3.60 GHz and above. Subsequent versions of the Prescott processor, including the 3.80 GHz in Q3 2004, and the 4.00 GHz in Q4 2004, will appear on the Socket-775 platform only, as will Prescott’s successor, Tejas, in 2005. All Prescott Pentium 4 processors will operate with an 800 MHz FSB, and will feature Hyper-Threading Technology (excluding the 2.80A GHz model, which uses a 533 MHz bus and no Hyper-Threading).At the low-end, Intel will continue to use the Socket-478 platform for its Celeron processor through 2004. Over the year, the Celeron will slowly ramp up to 3.33 GHz using the 90nm process, and continue to use the Socket-478 platform. It will eventually migrate to the Socket-775 platform as well near the end of the year. All 90nm Celerons will get a bump to 256kB of L2 cache.

Fig. 3 - Intel's current 2004 roadmaps suggest the above processors will be introduced in the timeframes indicated. The last Socket-478 Pentium 4 processor is the 3.40 GHz parts introduced today.

As an aside, these 90nm Celerons may be of some interest to overclockers. A 2.53 GHz (533 MHz FSB) Celeron using the 90nm process will be introduced in Q2 2004, and depending on its price and the maturity of the process at that point, may prove to be a capable overclocker.
Incremental Improvements
Beyond the previously discussed items, Prescott also contains several incremental improvements versus the previous Northwood core. We won’t discuss these in great detail, but rather summarize them briefly below:
Automated functional block design & strained silicon technology
Shifter/Rotator block added to one of the core’s double-speed ALUs
More flexible trace cache
Added a dedicated integer multiplier, which results in lower integer multiply latency.
Increased micro-op scheduler capacity
Improved hardware and software prefetching capability
Additionally, to clear up any confusion that may be caused by the marketing, the following table summarizes current Intel Pentium 4 processors that are available as of today.
Fig. 4 - Intel's current desktop processor lineup. These processors are available at retail and OEM levels as of the time of publication of this article.

Something Rotten in Santa Clara
Despite what seems to be a largely improved processor, and one that should easily outperform a Northwood-core Pentium 4 at equivalent clock speed, this is not the case. Further, there are some strong indications that there is something very seriously wrong with Intel’s 90nm process. Firstly, Prescott was delayed. Earlier roadmaps showed Prescott arriving at the end of 2003, which clearly hasn't been the case. Secondly, Prescott’s pipeline has been deepened versus Northwood’s (probably related to the delays) from 20 stages up to a whopping 31 stages. More importantly, signs indicate that this wasn’t a previously planned change, and Intel seems much less inclined to discuss it than is typically the case when these types of changes are made. From a company that prides itself on adhering to its roadmaps religiously, and that typically talks about these changes openly, this is some rather alarming behavior. Typically a process shrink like this would allow an almost instant boost in clockspeed. The last drop, from the 180nm Willamette down to the 130nm Northwood allowed an almost instant 20% boost in clockspeed, which worked its way up to over 60% as the process was refined. The final Northwood at 3.40GHz is 70% faster than the fastest Willamette as a result of the success of the 130nm process.This time, on the other hand, the drop to 90nm seems not to be resulting in the usual improvements. So much so, in fact, that a rather last-minute change to the pipeline was necessary to produce decent yields at the promised speeds. The longer pipeline will lower Prescott’s IPC, and largely offset any gains as a result of the improvements discussed. See our benchmarks for direct comparison. Some would no doubt argue that Intel is simply taking its time, and preparing for the future, as there's no imminent danger from AMD at the moment (which also seems to be having trouble with its 130nm strained silicon process - coincidence?). There may be some validity to that argument. Unfortunately at this point we can’t offer anything more than speculation. Intel’s public position is that everything is just fine, a 31-stage pipeline was all part of the plan, and it still promises 4GHz by year end. Yet its actions seem to indicate behind-the-scenes scrambling. Usually when there's this much whispering about problems, and such a tight-lipped reaction from the company, there's at least some truth to the speculation. We leave you to form your own conclusions.

Benchmark Configuration
Intel Pentium 4 Processor 3.20E GHz (Prescott)
Intel Pentium 4 Processor 3.06 GHz (Northwood)
Intel Desktop Board D875PBZ, 875 Chipset
512 MB (2 x 256 MB) PC3200 DDR Memory in Dual-Channel Configuration
ATI Radeon 9700 Pro
Western Digital WD400BB 40 GB Hard Disk
Creative Labs SoundBlaster Live!
Enermax EG465P-VE 460W Power Supply
Microsoft Windows XP Professional w/ Service Pack 1
Microsoft DirexctX 9.0
Intel Chipset Drivers v/ 5.00.1012
Intel Application Accelerator v/ 3.5.0.2600
ATI Catalyst 4.1

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Socket T

By : http://en.wikipedia.org/wiki/Socket_T

Socket T
Specifications
Type:LGA

Chip form factors:Flip-chip land grid array

Contacts:775

Bus Protocol


FSB:533 MT/s, 800 MT/s, 1066 MT/s, 1333MT/s

Voltage range


Processors:
Intel Pentium 4 (2.66 - 3.80 GHz)Intel Celeron D (2.53 - 3.6 GHz )Intel Pentium 4 Extreme Edition (3.20 - 3.73 GHz)Intel Pentium D (2.66 - 3.60 GHz)Intel Pentium Extreme Edition (3.20 - 3.73 GHz)Intel Core 2 Duo (1.60 - 2.67 GHz)Intel Core 2 Extreme (2.66 - 2.93 GHz)Intel Core 2 Quad (2.4 GHz)Intel Xeon (1.86-2.66 GHz)

Socket T, also known as LGA775, is Intel's latest desktop CPU socket. LGA stands for Land Grid Array. The word "socket" is now a misnomer, because an LGA775 motherboard has no socket holes, instead it has 775 protruding pins which touch contact points on the underside of the processor (CPU).
The Prescott and Cedar Mill Pentium 4 cores, as well as the Smithfield and Presler Pentium D cores, currently use the LGA775 socket type. In July 2006, Intel released the desktop version of the Core 2 Duo (codenamed Conroe), which also uses this socket, as does the subsequent Core 2 Quad. Intel changed from Socket 478 to LGA775 because the new pin type offers better power distribution to the processor, allowing the front side bus to be raised to 1333 MT/s. The 'T' in Socket T was derived from the now cancelled Tejas core, which was to replace the Prescott core.
As it is now the motherboard which has the pins, rather than the CPU, the risk of pins being bent is transferred from the CPU to the motherboard. The risk of bent pins is reduced because the pins are spring-loaded and locate onto a surface, rather than into a hole. Also, the CPU is pressed into place by a "load plate", rather than human fingers directly. The installing technician lifts the hinged "load plate", inserts the processor, closes the load plate over the top of the processor, and pushes down a locking lever. The pressure of the locking lever on the load plate clamps the processor's 775 gold contact points firmly down onto the motherboard's 775 pins, ensuring a good connection. The load plate only covers the edges of the top surface of the CPU; the center is free to make contact with the cooling mechanism placed on top of the CPU.

Improvements in Heat Dissipation
The force from the load plate ensures that the processor is completely level, giving the CPU's upper surface optimal contact with the heat sink or cold-water block fixed onto the top of the CPU to carry away the heat generated by the CPU. This socket also introduces a new method of connecting the heat dissipation interface to the chip surface and motherboard. With Socket T, the heat dissipation interface is connected directly to the motherboard on four points, compared with the two connections of the Socket 370 and the "clamshell" four-point connection of the Socket 478. This was done to avoid the reputed danger of the heatsinks/fans of pre-built computers falling off in transit. LGA775 was announced to have better heat dissipation properties than the Socket 478 it was designed to replace; but the Prescott core CPUs (in their early incarnations) ran much hotter than the previous Northwood-core Pentium 4 CPUs, and this initially neutralized the benefits of better heat transfer. However, modern Core 2 Duo processors run at lower temperatures than the Prescott CPUs they replace.

Socket T mechanical load limits
All socket T processors(Pentium 4, Celeron, Core 2 and Quad Xeon) have the following mechanical maximum load limits which should not be exceeded during heatsink assembly, shipping conditions, or standard use. Load above those limits will crack the processor die and make it unusable.

The transition to the LGA packaging has lowered those load limits, which are smaller than the load limits of Socket 478 processors but they are bigger than socket 370 and socket A processors which were fragile. They are large enough to ensure that processors will not crack.

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Socket P

By : http://en.wikipedia.org/wiki/Socket_P

Socket P

Socket P
Specifications
Type:PGA

Chip form factors:Flip-chip pin grid array

Contacts:478

Bus Protocol

FSB:400MT/s, 533 MT/s, 667 MT/s, 800MT/s

Voltage range


Processors:
Intel Core Solo,Intel Core Duo,Intel Dual-Core Xeon (1.67, 2.0),Intel Core 2 Duo, (T5x00, T7x00),Intel Celeron M (Penryn, Merom)

The Intel Socket P is the mobile processor socket replacement for the new Intel Core 2 chips. It has an 800 MT/s FSB, that is switchable on the fly to 400MT/s to save power. It launched on May 9, 2007, as part of the Santa Rosa platform. Socket P has 478 pins, but is not pin-compatible with Socket M.

Processors
Celeron M 540
Core 2 Duo T7100
Core 2 Duo T7300
Core 2 Duo T7500
Core 2 Duo T7700
Rumored to use this socket:
Core 2 Duo X7800 (2.6 GHz)
Core 2 Duo X7900 (2.8 GHz)

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Socket 478

By :http://en.wikipedia.org/wiki/Socket_478

Socket 478
Specifications
Type :PGA-ZIF

Chip form factors:Flip-chip pin grid array (FC-PGA2 or FC-PGA4)

Contacts:478

Bus Protocol:AGTL+

FSB:400 MT/s533 MT/s800 MT/s

Voltage range


Processors :
Intel Pentium 4 (1.4 - 3.4 GHz)Intel Celeron (1.7 - 2.8 GHz)Celeron D (2.13 - 3.2 GHz)Intel Pentium 4 Extreme Edition (3.2, 3.4 GHz)

In computing, Socket 478 is a type of CPU socket used for Intel's Pentium 4 and Celeron series CPUs. Socket 478 was phased out with the launch of LGA775.
Socket 478 has been used for all of the Northwood Pentium 4s and Celerons, the first Prescott Pentium 4s, and some Willamette Celerons and Pentium 4s. Socket 478 also supports newer Prescott Celeron Ds, and early Pentium 4 Extreme Edition processors with 2MB of L3 cache and some Core Duos. The socket was launched with the Northwood core to compete with AMD's 462-pin Socket A and their Athlon XP processors. Socket 478, which accommodates high and low-end processors, was also the replacement for Socket 423, a Willamette processor socket which remained in the market for only a short time.
Motherboards that use this socket support DDR, RDRAM, and in some cases SDRAM. However, the majority of boards are DDR based. Initial motherboards only supported RDRAM, however RDRAM is quite expensive, compared to DDR and SDRAM, and consumers demanded an alternative, thus DDR and SDRAM boards were made. Later revisions to chipsets that support Socket 478 added higher FSB speeds, higher DDR speeds, and support for dual channel DDR.
Like the previous Socket 423, Socket 478 is based on Intel's Quad Data Rate technology, with data transferring at four times the clock rate of its Front Side Bus. As such, the 400 MT/s bus was based on a 100 MHz clock signal, but was still able to provide 3.2GB/s of data to the chipset. At its release, no SDRAM product was capable of supporting so high a data rate, so Intel pushed forward RDRAM technology, with two channels of PC800 providing synchronous data capability. Poor consumer acceptance of expensive RDRAM lead Intel to release low-performance PC133-supporting chipsets, and finally DDR chipsets.
While the original 400 MT/s bus matched the data rate of PC3200, this bus speed was already outdated by the time PC3200 became available. Dual-channel memory was introduced on later chipsets, so that a matched pair of PC3200 modules was able to match the final 800 MT/s FSB.
The Celeron D is also available for Socket 478 and they are now the only CPU's still made for the socket. They use a quad-pumped 133MHz Bus Giving A 533MT/s FSB. They are available with 256KB L2 Cache and are built on the 90nm manufacturing process, using the Prescott Core.
Socket 478 is officially known by Intel as FC-PGA2 [1]. While Core Duo is available in a 478-pin package, that socket is different: micro FC-PGA [2], which was also used for earlier Pentium M and Celeron M processors. Core Duo is also available in a 479-ball (not pin) package known as micro FC-BGA.
Socket 478 mechanical load limits
All socket 478 processors(Pentium 4 and Celeron) have the following mechanical maximum load limits which should not be exceeded during heatsink assembly, shipping conditions, or standard use. Load above those limits will crack the processor die and make it unusable.

LocationDynamicStaticTransientIHS Surface

890 N(200 lbf)
445 N(100 lbf)
667 N(150 lbf)

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Socket 423

By : http://en.wikipedia.org/wiki/Socket_423

SpecificationsTypePGA-ZIF

Chip form factorsOrganic Land Grid Array (OLGA) on Interposer (OOI) (INT2 and INT3)

Contacts
423
Bus ProtocolAGTL+

FSB100 MHz FSB(equivalent to FSB400 (Quad data rate))

Voltage range1.0 - 1.85 V

ProcessorsIntel Pentium 4 (1300 MHz - 2000 MHz)


Socket 423
Socket 423 was a CPU socket used for the first Pentium 4 processors, based on the Willamette core. The socket was short-lived, as it became apparent that its electrical design proved inadequate for raising clock speed beyond 2.0 GHz. Intel produced chips using this socket for less than a year, from November 2000 to August 2001. It was replaced by Socket 478.
The "PowerLeap PL-P4/N" is a device developed in the form of a socket adapter allowing the use of socket 478 processors on the socket 423.
Along with the socket these CPUs use (and therefore the motherboards), there is another short lived and odd piece of hardware: the RAM. The type of RAM used on some of these motherboards is RDRAM. This type of RAM is now very expensive, ranging from $US54 for 128MB to $US214 for 512MB. These sticks of RAM also must be used in pairs similar to modern dual channel memory.

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Xeon

By : http://en.wikipedia.org

Xeon

The Xeon brand refers to Intel's x86 multiprocessing CPUs - for dual-processor (DP) and multi-processor (MP) configuration on a single motherboard (like AMD's Athlon MP and Opteron branded processors) - targeted at non-consumer markets of server and workstation computers, and also at blade servers and embedded systems. The Xeon brand has been maintained over several generations of x86 and x86-64 processors. Older models added the Xeon moniker to the end of the name of their corresponding desktop processor, but more recent models used the name Xeon on its own. The Xeon CPUs generally have more cache than their desktop counterparts in addition to multiprocessing capabilities. Intel's (non-x86) IA-64 processors are called Itanium, not Xeon.

Pentium II Xeon
The first Xeon branded processor was released in 1998, named the Pentium II Xeon (codenamed "Drake"), as the replacement of the Pentium Pro. It was based on the 0.25 µm "Deschutes" core (P6 microarchitecture) branded Pentium II (sharing its 80523 product code), used either a 440GX (a dual-processor workstation chipset) or 450NX (quad-processor, or oct with additional logic) chipset, and differed from the Pentium II desktop CPU (Deschutes) in that its off-die L2 cache ran at full speed. It also used a larger slot known as slot 2. Cache sizes were 512 KB, 1 MB and 2 MB, and it used a 100 MT/s front side bus (FSB).

Pentium III Xeon
In 1999, the Pentium II Xeon was replaced by the Pentium III Xeon. The initial version, "Tanner", was just like its predecessor except for the addition of Streaming SIMD Extensions (SSE) and a few cache controller enhancements found in the "Katmai" Pentium III. The second version, the "Cascades", was based on the "Coppermine" core branded Pentium III. The Cascades had a 133 MT/s bus and only a 256 KB on-die L2 cache resulting in almost the same capabilities, as the Coppermine desktop Slot 1 versions (branded Pentium III) also capable of dual-processor operation, but not only quad-processor operation. To improve this situation, Intel released another version, officially also named "Cascades", but often referred to as "Cascades 2 MB". That came in two variants: with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MT/s, though in practice the cache was able to offset this. Product codes for Tanner and Cascades mirrored that of Katmai and Coppermine; 80525 and 80526 respectively.

Xeon (DP) & Xeon MP (32-bit)
In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new NetBurst architecture, "Foster", was slightly different from the desktop Pentium 4 ("Willamette"). It was a decent chip for workstations, but for server applications it was almost always outperformed by the older Cascade 2 MB core and AMD's Athlon MP. Combined with the need to use expensive Rambus Dynamic RAM, the Foster's sales were somewhat unimpressive.
At most two Foster processors could be accommodated in an SMP system built with a mainstream chipset, so a second version (Foster MP) was introduced with a 1 MB L3 cache and the Jackson Hyper-Threading capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions.
In 2002 Intel released a 130 nm version of Xeon branded CPU, codenamed "Prestonia". It supported Intel's new Hyper-Threading technology and had a 512 KB L2 cache. This was based on the "Northwood" Pentium 4 core. A new server chipset, E7500 (which allowed the use of dual-channel DDR SDRAM) was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by new chipsets: the E7501 for servers and the E7505 for workstations). The Prestonia performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.
Subsequent to the Prestonia was the "Gallatin", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version also performed much better than the Foster MP, and was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP branded Gallatin with 4 MB cache.
The Foster shared the 80528 product code with Willamette; The Xeon branded Prestonia and Gallatin were designated 80532, like Northwood.

Xeon (DP) & Xeon MP (64-bit)

Due to a lack of success with Intel's Itanium and Itanium 2 processors, the 90 nm version of the Pentium 4 (""Prescott") was built with support for 64-bit instructions (called Intel 64, Intel's implementation of x86-64), and a Xeon version codenamed "Nocona" was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for PCI Express, DDR-II and Serial ATA. The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play.
A slightly updated core called "Irwindale" was released in early 2005, with twice the L2 cache of Nocona and able to reduce its clockspeeds during low processor demand. However, independent tests showed that AMD's Opteron still outperformed Irwindale.
64-bit Xeon MPs were introduced in April 2005. The cheaper "Cranford" was an MP version of Nocona, while the more expensive "Potomac" was a Cranford with 8 MB of L3 cache. All these Prescott-derived Xeons have the product code 80546.

Dual-Core Xeon

"Paxville DP"
The first dual-core CPU branded Xeon, codenamed Paxville DP, product code 80551, was released by Intel on 10 October 2005. Paxville DP had NetBurst architecture, and was a dual-core equivalent of the single-core Irwindale (related to the Pentium D branded "Smithfield") with 4 MB of L2 Cache (2 MB per core). The only one Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a 90 nm process.

7000-series "Paxville MP"
An MP-capable version of Paxville DP, codenamed Paxville MP, product code 80560, was released on 1 November 2005. There are two versions: one with 2 MB of L2 Cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2.67 and 3.0 GHz (model numbers 7020-7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.

LV (ULV), "Sossaman"
On 14 March 2006, Intel released a dual-core processor codenamed Sossaman and branded as Xeon LV (low-voltage). Subsequently an ULV (ultra-low-voltage) version was released. The Sossaman was a low-/ultra-low-power and double-processor capable CPU (like AMD Quad FX), based on the "Yonah" processor, for ultradense non-consumer environment (i.e. targeted at the blade-server and embedded markets), and it was rated at a thermal design power (TDP) of 31 watts (LV: 1.66 and 2 GHz ) and 15 W (ULV: 1.66 GHz)[1]. As such, it supported most of the same features as earlier Xeons - Virtualization Technology, 667 MT/s front side bus, and dual-core processing, but it did not support 64-bit operations, so it could not run 64-bit-only server software, such as Microsoft Exchange Server 2007, and - so - it was limited to only 16 GB of memory. A planned successor, codenamed "Merom MP" was to be a drop-in upgrade to allow Sossaman-based servers to upgrade to 64-bit capability. However, this was abandoned in favour of low-voltage versions of the Woodcrest LV processor leaving the Sossaman at a dead-end with no planned upgrades.

5000-series "Dempsey"
On 23 May 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed Dempsey (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is a NetBurst architecture processor produced using a 65 nm process, and is virtually identical to Intel's "Presler" Pentium Extreme Edition, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.67 and 3.73 GHz (model numbers 5030-5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MB of L2 Cache (2 MB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: Socket J, also known as LGA 771.

5100-series "Woodcrest"
On 26 June 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamed Woodcrest (product code 80556); it was the first Intel Core microarchitecture processor to be launched on the market. It is a server and workstation version of the Intel Core 2 processor. Intel claims that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the Pentium D.

It has a 1333 MT/s FSB in most models, except for the 5110 and 5120, which have a 1066 MT/s FSB, with the fastest processor clocking in at 3.0 GHz. All Woodcrests use LGA 771 and all but the 5160 and 5148LV have a TDP of 65 W, which is much less than the previous generation of 130 W. The 5160 has a TDP of 80 W, still much less than 130 W, and the 5148LV, has a TDP of 40 W. All models support Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, with Demand-Based Switching only on Dual-Core Xeon 5140 or above. Woodcrest has 4 MiB of shared L2 Cache.

7100-series "Tulsa"
Released on 29 August 2006 , the 7100 series, codenamed Tulsa (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MiB of L2 cache (1 MiB per core) and up to 16 MiB of L3 cache. It uses Socket 604 . Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 to 3.5 GHz (model numbers 7110N-7150N), and the M-line ranges from 2.6 to 3.4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MiB to 16 MiB across the models.

7300-series "Tigerton"
The 7300 series, codenamed Tigerton will be a quad-core, MP-capable processor to be released in place of Whitefield. It is expected to ship in the second half of 2007.

3000-series "Conroe"
The 3000 series, codenamed Conroe (product code 80557) dual-core Xeon (branded) CPU, released at the end of September 2006, was just rebranded version of the Intel's mainstream Conroe otherwise branded as Core 2 Duo (for consumer desktops). Unlike most Xeon processors, they only support single-CPU operation. They use Socket T (LGA775), operate on a 1066 MHz front-side bus, and do not support Hyper-Threading. Processors with a number ending in "5" have a 1333 MT/s FSB.

Quad-Core Xeon

5300-series "Clovertown"

A quad-core successor of Woodcrest for DP segment, consisting of two Woodcrest chips in one package similar to the Pentium D Presler or quad-core Kentsfield. The Clovertown has been usually implemented with two Woodcrest dies on a multi-chip module, with 8 MiB of L2 cache (4 MiB per die). Like Woodcrest, lower models use a 1066 MT/s FSB, and higher models use a 1333 MT/s FSB. Intel released Clovertown, product code 80563, on 14 November 2006 [9] with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6 to 2.66 GHz. The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066 MT/s FSB, and an ending of -5 implies a 1333 MT/s FSB. All models have a TDP of 80 W with the exception of the X5355, which has a TDP of 120 W. A low-voltage version of Clovertown with a TDP of 50 W has a model numbers L5310 and L5320 (1.6 and 1.86 GHz respectively). The 3.0 GHz X5365 was expected in July 2007, and became available in the Apple Mac Pro [11] on 4 April 2007.

3200-series "Kentsfield"
Intel released relabeled versions of its quad-core Core 2 Quad processor as the Xeon 3200-series on 7 January 2007. The models are the X3210, X3220 and X3230, running at 2.13, 2.4 and 2.66 GHz, respectively. Like the 3000-series, these models only support single-CPU operation and operate on a 1066 MHz front-side bus.

Future versions

Whitefield (cancelled)

A quad-core processor, partially based on Woodcrest, and would have used the new Common System Interface (CSI) bus, a bus shared with the Itanium 2 processors of its generation (beginning with the "Tukwila" core). Whitefield would have had 16 MiB of L2 cache, manufactured using the 65 nm process initially, and the 45 nm process later.
Whitefield was the first full processor being worked on at Whitefield, Bangalore, India. It was cancelled from the processor roadmap and replaced with Tigerton.

Aliceton

Aliceton was a successor to Tigerton. It has effectively been renamed Dunnington as the original Dunnington was based on the now cancelled Whitefield.

Dunnington

A 45 nm successor to Tigerton (formerly Aliceton), a four to eight (likely six) core processor [19] [20]. Dunnington was originally based on Whitefield, but with Whitefield cancelled, Dunnington's details are less clear.
Harpertown
Harpertown is said to be a 45 nm, eight-core processor with 12 MiB of L2 cache. An older rumour stated that it was simply the 45 nm shrink of Woodcrest, but that has since changed. Harpertown, which will succeed the current 65 nm Clovertown processors (Xeon 5300 series), will receive 5400 sequence number, with X, E, and L letters indicating performance, regular and low-power versions of the CPU.
The mainstream lineup (80 watts) will reach from the E5405 with a clock speed in the low 2 GHz range up to the E5450 with 3.0 GHz. The X5460 will clock in at 3.16 GHz and will be rated at a thermal design power of 120 watts. Intel also plans to introduce two low-power versions, rated at 50 watts, with 2.33 and 2.66 GHz speeds (L5410 and L5430). All Harpertown processors will include a 12 MB L2 cache, up from 8 MB in Clovertown. The front side bus is expected to be a FSB1333 version across the board, while the slide published by VR-Zone still indicates that the E5405 could run at a slower clock speed.
The dual-core version of the CPU, code-named Wolfdale, apparently will be available with processor speeds of 1.86 GHz and 3.33 GHz (both rated at 65 watt TDP). There will also be a 3.16 GHz low-power version of the processor, running at 40 watts.

Harpertown and Wolfdale are expected to launch late in Q4 of this year(2007).

Gainestown
Gainestown is a quad-core processor based on Intel's upcoming Nehalem microarchitecture.

Beckton
Nehalem-based MP-capable processor.

Supercomputers

Supercomputers based on Xeon processors in the top 10 of the Top500 fastest supercomputers in the world:
Thunderbird, at Sandia National Laboratories. Machine: Dell PowerEdge 1850 Cluster. CPU: 9,024 Xeons (3.6 GHz). Connection: InfiniBand. Rmax: 38.27 Teraflops. (number 5 as of November 2006, ahead of the fastest Itanium-based supercomputers but behind three PPC-based systems and one Opteron system.)

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Intel Itanium

By : http://en.wikipedia.org

Itanium
Itanium 2

Produced:
From mid 2002 to present
Manufacturer:Intel
CPU Speeds:733 MHz to 1.6 GHz
FSB Speeds:200 MHz to 533 MHz
Instruction Set:Itanium
Socket:PAC611
Cores:
· McKinley
· Madison
· Hondo
· Deerfield
· Montecito

Itanium is the brand name for 64-bit Intel Microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel has released two processor families using the brand: Itanium and Itanium 2. The processors are marketed for use in enterprise servers and high-performance computing systems. The architecture originated at Hewlett-Packard (HP) which was then later developed by HP and Intel together.
Itanium's architecture differs dramatically from the x86 and x86-64 architectures used in other Intel processors. The architecture is based on explicit instruction-level parallelism, with the compiler making the decisions about which instructions to execute in parallel. This approach allows the processor to execute up to six instructions per clock cycle. By contrast with other superscalar architectures, Itanium does not need elaborate hardware to keep track of instruction dependencies during parallel execution.
After a protracted development process, the first Itanium was released in 2001, and subsequently more powerful Itanium processors have been released periodically. HP produces most Itanium-based systems, but several other manufacturers have also developed systems based on Itanium. As of 2007, Itanium is the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, IBM POWER, and SPARC. After a schedule slip of several years,Intel released its newest Itanium 2, codenamed Montecito, in July 2006.
Development: 1989–2001
In 1989, HP determined that reduced instruction set computer (RISC) architectures were approaching a processing limit at one instruction per cycle. HP researchers investigated a new architecture called Explicitly Parallel Instruction Computing (EPIC) that allows the processor to execute multiple instructions in one clock cycle. EPIC implements a form of very long instruction word (VLIW) architecture, where one instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel.
HP determined that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so HP partnered with Intel in 1994 to develop the IA-64 architecture, which derived from EPIC. Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of the enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, codenamed Merced, in 1998.
During development, Intel, HP, and industry analysts were predicting that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computer (CISC) architectures for all general-purpose applications. Several groups began to develop operating systems for the architecture, including Microsoft Windows variants, Linux variants, and UNIX variants. By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of the Merced began slipping quarter by quarter.Technical difficulties included the very high transistor counts needed to support the wide instruction words and the large caches. There were also structural problems within the project, as the two parts of the joint team used different methodologies and had slightly different priorities. Since Merced was the first EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depends on compiler capabilities that had never been implemented before, so more unanticipated research was needed.
Intel announced the official name of the processor, Itanium, on October 4, 1999.Within hours observers referred to the processor as Itanic,a reference to Titanic, the "unsinkable" ocean liner which sank in 1912. Itanic has since often been used by The Register,Scott McNealy,and others It alludes to the perception that Itanium is a white elephant which cost Intel and HP many billions of dollars while failing to achieve expected performance and sales in the originally projected timeframe. Meanwhile, RISC and CISC architects were making steady improvements in superscalar implementations, allowing them to break the one-instruction-per-clock barrier without using EPIC.

Itanium processor: 2001–02

Intel Itanium processor
Produced:
From June 2001 to June 2002
Manufacturer:Intel
CPU Speeds:733 MHz to 800 MHz
FSB Speeds:266 MT/s to 266 MT/s
Instruction Set:Itanium
Socket:PAC418
Core Name:Merced

By the time Itanium was released in June, 2001, it was no longer superior to contemporaneous RISC and CISC processors. Itanium competed at the low-end (primarily 4-CPU and smaller systems) with servers based on x86 processors, and at the high end with IBM's POWER architecture and Sun Microsystems' SPARC architecture. Intel repositioned Itanium to focus on high-end business and HPC computing, attempting to duplicate x86's successful "horizontal" (i.e., single architecture, multiple systems vendors) market. Its success was limited to replacing PA-RISC and Alpha in HP systems and MIPS in SGI's HPC systems. POWER and SPARC remained strong, while the 32-bit x86 architecture grew into the enterprise space. With economies of scale fueled by its enormous installed base, x86 was the preeminent "horizontal" architecture in enterprise computing. HP and Intel recognized that Itanium was not competitive and replaced it with Itanium 2 a year later, as they had planned. Only a few thousand of the original Itaniums were sold, due to limited availability caused by poor yields, relatively poor performance, and high cost. However, these machines were useful for software development for the Itanium 2 processors that followed. IBM delivered a supercomputer based on this processor.[12]
Itanium 2 processors: 2002–present
The Itanium 2 was released in 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The initial Itanium 2 was codenamed McKinley. McKinley used a 180 nm process, but it relieved many of the performance problems of the original Itanium. In 2003, AMD released the Opteron, which implemented its x86-64 64-bit architecture. Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from x86. Intel responded by implementing x86-64 in its Xeon microprocessors in 2004 Intel released a new Itanium 2 family member, codenamed Madison, in 2003. Madison used a 130 nm process and was the basis of all new Itaniums until Montecito was released in June 2006.
In March, 2005, Intel announced that it was working on a new Itanium device, codenamed Tukwila, to be released in 2007. Tukwila would have four processors and would replace the Itanium bus with a new Common System Interface, which would also be used by a new Xeon.Intel later said that Tukwila would be delivered in late 2008.
In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate software portingThe Alliance announced that its members would invest $10 Billion in Itanium solutions by the end of the decade. As of June 2007, Intel has released seven additional versions of the Itanium 2, and another is expected in late 2007.
Architecture
the Itanium instruction set and microarchitecture, and the technical press has provided overviews.The architecture has been renamed several times during its history. HP called it EPIC and renamed it to PA-WideWord. Intel later called it IA-64, before settling on Intel Itanium Architecture, but it is still widely referred to as IA-64. It is a 64-bit register-rich explicitly-parallel architecture. The base data word is 64 bits, byte-addressable. The logical address space is 264 bytes. The architecture implements predication, speculation, and branch prediction. It uses a hardware register renaming mechanism rather than simple register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.
The architecture implements 128 integer registers, 128 floating point registers, 64 one-bit predicates, and eight branch registers. The floating point registers are 82 bits long to preserve precision for intermediate results.
Instruction execution
Each 128-bit instruction word contains three instructions, and the fetch mechanism can read up to two instruction words per clock from the L1 cache into the pipeline. When the compiler can take maximum advantage of this, the processor can execute six instructions per clock cycle. The processor has thirty functional execution units in eleven groups. Each unit can execute a particular subset of the instruction set, and each unit executes at a rate of one instruction per cycle unless execution stalls waiting for data. While not all units in a group execute identical subsets of the instruction set, common instructions can be executed in multiple units. The groups are:
Six general-purpose ALUs, two integer units, one shift unit
Four data cache units
Six multimedia units, two parallel shift units, one parallel multiply, one population count
two floating-point multiply-accumulate units, two "miscellaneous" floating-point units
three branch units
Thus, the compiler can often group instructions into sets of six that can execute at the same time. Since the floating-point units implement a multiply-accumulate operation, a single floating point instruction can perform the work of two instructions when the application requires a multiply followed by an add: this is very common in scientific processing. When it occurs, the processor can execute four FLOPs per cycle.
Memory architecture
From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KiB of Level 1 instruction cache and 16 KiB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KiB. The Level 3 cache was also unified and varied in size from 1.5 MiB to 24 MiB. The 256 Kib L2 cache contains sufficient logic to handle semaphore operations without disturbing the main arithmetic logic unit (ALU).
Main memory is accessed through a bus to an off-chip chipset. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to by Intel's official name: the Scalability Port. The speed of the bus has increased steadily with new processor releases. The bus transfers 2x128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GB/s and the 533 MHz Montecito bus transfers 17.056 GB/s.
Architectural changes
Itaniums released prior to 2006 had hardware support for the IA-32 architecture to permit support for legacy server applications, but performance was much worse in comparison with native instruction performance and contemporaneous x86 processors. In 2005 Intel developed a software emulator that provided better performance. With Montecito, Intel removed IA-32 support from the hardware.
With Montecito, Intel made enhancements to the architecture in July 2006 The architecture now includes hardware multithreading: each processor maintains context for two threads of execution. When one thread stalls due to a memory access the other thread gains control. Intel calls this "coarse multithreading" to distinguish it from "hyperthreading technology" that was used in some x86 and x86-64 microprocessors. Coarse multithreading is well matched to the Intel Itanium Architecture and results in an appreciable performance gain. Intel also added hardware support for virtualization. Virtualization allows a software "hypervisor" to run multiple operating system instances on the processor concurrently. Montecito also features a split L2 cache, adding a dedicated 1 MiB L2 cache for instructions and converting the original 256 KiB L2 cache to a dedicated data cache.

As of 2007, several manufacturers offer Itanium 2 based systems, including HP, SGI, NEC, Fujitsu, Unisys, Hitachi, and Groupe Bull. In addition, Intel offers a chassis[20] that can be used by system integrators to build Itanium systems. HP, the only one of the industry's top four server manufacturers to offer Itanium-based systems today, manufactures at least 80% of all Itanium 2 systems. HP sold 7200 systems in the first quarter of 2006.[21] The bulk of the sales are of enterprise servers and machines for large-scale technical computing, with an average selling price per system in excess of US $200,000. A typical system uses eight or more Itanium processors.
Chipsets
The Itanium bus interfaces to the rest of the system via a chipset. Enterprise server manufacturers differentiate their systems by designing and developing chipsets that interface the processor to memory, interconnections, and peripheral controllers. The chipset is the heart of the system-level architecture for each system design. Development of a chipset costs tens of millions of dollars and represents a major commitment to the use of the Itanium. Currently, modern chipsets for Itanium are manufactured by HP, Fujitsu, SGI, NEC, Hitachi, and Unisys. IBM created a chipset in 2003, and Intel in 2002, but neither of them has developed chipsets to support newer technologies such as DDR2 or PCI Express.

Processors

The Itanium processors show a steady progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt.The future of the Itanium family apparently lies in multi-core chips, based on available information about coming generations. The final products will most likely bear the Itanium 2 brand, or possibly Itanium 3. As of June 2007, some information is known for the following:
Montvale will be a revision of Montecito bringing slightly higher clock speeds (to 1.66Ghz), larger L3 caches (to 24MiB), and a faster FSB (to 667Mhz). The processor will implement a new power-saving system. Montvale will comprise a set of six variants called the Itanium 2 9100 series. Release is expected at the end of 2007. The processors were originally expected to be released in June 2007, a year after Montecito.
Tukwila, the first 65 nanometer design, is due in late 2008. Tukwila will include four cores, large on-die caches, Hyper-Threading technology and an integrated memory controller. A key feature of Tukwila is double-device data correction, which helps to fix memory errors. Poulson will use a 32 nm process and will feature four or more cores, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization. For Kittson, few details are known other than the existence of the codename.

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